Class 257/E21.409 - With an insulated gate (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.4. This subclass
No. of patents: 92
Last issue date: 07/29/2008

«First «Previous1 2 3 Next»Last»

Number	Title	Issue Date
7405116	Application of gate edge liner to maintain gate length CD in a replacement gate transistor flow A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selectiv...	07/29/2008
7396727	Transistor of semiconductor device and method for fabricating the same A transistor which may effectively control the short channel effect with a vertical transistor structure. This structure may prevent the degradation of a transistor's performance caused by the hot carrier effect. The transistor has a source region having a concentra...	07/08/2008
7368336	Organic insulator, organic thin film transistor array panel including organic insulator, and manufacturing method therefor An insulating film according to an embodiment of the present invention has Chemical Formula 1 wherein the Rs are equal to or different from each other, m is an integer, the Rs have Chemical Formula ...	05/06/2008
7320910	Semiconductor device Manufacturing of semiconductor device includes forming, at substrate main surface, PMOS and NMOS regions separated by PN film. Polysilicon is formed at surface. First insulating film serves as gate insulating film. Second insulating film is formed on polysilicon sur...	01/22/2008
7316960	Strain enhanced ultra shallow junction formation Provided is a method of manufacturing a microelectronic device. In one example where the device includes a semiconductor substrate with a gate feature and a shallow junction, the method includes introducing dopants to the substrate to form a source region and a drai...	01/08/2008
7312501	Semiconductor device ON resistance and leakage current of a vertical power MOSFET are to be diminished. In a vertical high breakdown voltage MOSFET with unit MOSFETs (cells) arranged longitudinally and transversely over a main surface of a semiconductor substrate, the cells are made qua...	12/25/2007
7282413	Semiconductor device including nonvolatile memory and method for fabricating the same A semiconductor device including a nonvolatile memory and the fabrication method of the same is described formed on a semiconductor substrate. According to the semiconductor device, a second gate electrode film is used for a gate electrode film of a logic circuit, a...	10/16/2007
7273772	Method for manufacturing thin film transistor array panel The present invention relates to a method of manufacturing a thin film transistor array panel and apparatus and more particularly to an apparatus containing an in-situ fluorine generation chamber. ...	09/25/2007
7271064	Method of forming a field effect transistor using conductive masking material The invention includes methods of forming field effect transistors. In one implementation, a method of forming a field effect transistor having a gate comprising a conductive metal or metal compound received over conductively doped semiconductive material includes f...	09/18/2007
7268025	Pixel structure and fabricating method thereof A pixel structure and a fabricating method thereof are described. The method comprises forming a conductive layer, a data line and a source/drain at the same time. The conductive layer has a coupling portion and a connecting portion. The coupling portion is used as ...	09/11/2007
7238578	Method of forming a semiconductor structure comprising transistor elements with differently stressed channel regions A semiconductor structure comprising a first transistor element and a second transistor element is provided. Stress in channel regions of the first and the second transistor element is controlled by forming stressed layers having a predetermined stress over the tran...	07/03/2007
7226822	Wiring material, semiconductor device provided with a wiring using the wiring material and method of manufacturing thereof By using a high purity target as a target, using a single gas, argon (Ar), as a sputtering gas, setting the substrate temperature at 300° C. or less, setting the sputtering power from 1 kW to 9 kW, and setting the sputtering gas pressure from 1.0 Pa to 3.0 Pa, the ...	06/05/2007
7217668	Gate technology for strained surface channel and strained buried channel MOSFET devices A method of fabricating a semiconductor device including providing a semiconductor heterostructure, the heterostructure having a relaxed Si1-xGex layer on a substrate, a strained channel layer on the relaxed Si1-xGex layer...	05/15/2007
7164163	Strained transistor with hybrid-strain inducing layer A semiconductor device having a hybrid-strained layer and a method of forming the same are discussed. The semiconductor device comprises: a gate dielectric over a substrate; a gate electrode over the gate dielectric; an optional pair of spacers along the sidewalls o...	01/16/2007
7160769	Channel orientation to enhance transistor performance P channel transistors are formed in a semiconductor layer that has a (110) surface orientation for enhancing P channel transistor performance, and the N channel transistors are formed in a semiconductor layer that has a (100) surface orientation. To further provide ...	01/09/2007
7122483	Gate technology for strained surface channel and strained buried channel MOSFET devices A method of fabricating a semiconductor device including providing a semiconductor heterostructure, the heterostructure having a relaxed Si1-xGex layer on a substrate, a strained channel layer on the relaxed Si1-xGex layer...	10/17/2006
7098098	Methods for transistors formation using selective gate implantation Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a...	08/29/2006
6794713	Semiconductor device and method of manufacturing the same including a dual layer raised source and drain SiGe or SiC films are selectively grown on source/drain regions, followed by selectively growing silicon. A monocrystalline film having a high dislocation density or a polycrystalline film can be grown in growing the silicon film by making the C or Ge concentration ...	09/21/2004
6670250	MOS transistor and method for forming the same A MOS transistor including a gate poly oxide layer formed to have different thicknesses over the entire surface of a semiconductor substrate and a method for forming the MOS transistor are provided. A gate oxide layer pattern and a gate conductive layer p...	12/30/2003
6638802	Forming strained source drain junction field effect transistors By providing a high dose germanium implant and then forming a P-type source/drain extension, a strained source/drain junction may be formed. The strained source/drain junction may be shallower and have lower resistivity in some embodiments....	10/28/2003
6630710	Elevated channel MOSFET The present invention provides a semiconductor device (e.g., MOSFET) having a channel above the surface of the wafer containing a well and a junction. The elevated channel may be selectively epitaxially grown and enables higher mobility, thereby enabling ...	10/07/2003
6627488	Method for fabricating a semiconductor device using a damascene process Disclosed herein is a method of fabricating a semiconductor device using a damascene process. The method comprises the steps of: forming a dummy gate electrode on a semiconductor substrate; forming a source/drain region in the substrate; polishing and pla...	09/30/2003
6613637	Composite spacer scheme with low overlapped parasitic capacitance A method and composition for a composite spacer with low overlapped capacitance includes a low-k dielectric spacer layer. A first spacer is deposited on a partially formed semiconductor device having a gate oxide stack, followed by a low dielectric consta...	09/02/2003
6580137	Damascene double gated transistors and related manufacturing methods This invention provides the structure and fabrication process of a completely planar, Damascene double gated transistor. The structure has a novel self-aligned, hyper-abrupt retrograde body and a zero-parasitic, endwall gate-body connection. The structure...	06/17/2003
6507091	Transistor with indium-implanted SiGe alloy and processes for fabricating the same An indium-implanted transistor is provided. The transistor has a silicon channel region that includes a buried layer of an Si1-x Gex alloy into which indium is implanted, with 10-5ࣘxࣘ4×10.sup.-1. A first method for ...	01/14/2003
6486520	Structure and method for a large-permittivity gate using a germanium layer A structure for, and method of forming, a metal-insulator-semiconductor field-effect transistor in an integrated circuit is disclosed. The disclosed method comprises forming a germanium layer 52 on a semiconductor substrate (e.g. silicon 20), depositing a...	11/26/2002
6432784	Method of forming L-shaped nitride spacers The disclosure includes an exemplary embodiment which relates to a method of forming L-shaped spacers in an integrated circuit. This method can include providing a gate structure over a semiconductor substrate, depositing a spacer material adjacent latera...	08/13/2002
6355543	Laser annealing for forming shallow source/drain extension for MOS transistor A method for making a ULSI MOSFET chip includes forming a transistor gate on a substrate and defining the contours of shallow source/drain extensions by implanting a first pre-amorphization (PAI) substance into the substrate. A sidewall spacer is then for...	03/12/2002
6350637	Method of fabrication of a no-field MOS transistor Method of fabrication of a no-field transistor with no extra process costs, providing for defining an active area for the transistor surrounded by a thick field oxide layer, insulatively placing a polysilicon gate electrode across the active area to defin...	02/26/2002
6350696	Spacer etch method for semiconductor device Spacers are formed on a semiconductor device by depositing a spacer layer on the semiconductor device. The semiconductor device is subjected to an anisotropic etching process to leave at least a portion of the spacer layer covering the semiconductor devic...	02/26/2002
6323525	MISFET semiconductor device having relative impurity concentration levels between layers A semiconductor device having a MISFET with an EV source/drain structure has a gate electrode formed on part of a first p-type semiconductor layer via a gate insulating film. A second n+ -type semiconductor layer is formed in the prospective so...	11/27/2001
6313512	Low source inductance compact FET topology for power amplifiers A field effect transistor (FET) comprising a plurality of drain finger electrodes, source finger electrodes and gate finger electrodes disposed in an active region of a semiconductor substrate; a drain bus disposed outside the active region and electrical...	11/06/2001
6274894	Low-bandgap source and drain formation for short-channel MOS transistors A transistor having source and drain regions which include lower-bandgap portions and a method for making the same are provided. A gate conductor is formed over a gate dielectric on a semiconductor substrate. The gate conductor is covered on all sides wit...	08/14/2001
6271551	Si-Ge CMOS semiconductor device To obtain a high mobility and a suitable threshold voltage in MOS transistors with channel dimensions in the deep sub-micron range, it is desirable to bury a strongly doped layer (or ground plane) in the channel region below a weakly doped intrinsic surfa...	08/07/2001
6235560	Silicon-germanium transistor and associated methods A method for making a transistor includes the steps of providing a silicon substrate including a silicon-germanium epitaxial layer, forming a masking implant layer on a channel region of the silicon-germanium epitaxial layer, and implanting dopants into t...	05/22/2001
6187641	Lateral MOSFET having a barrier between the source/drain region and the channel region using a heterostructure raised source/drain region A MOSFET (100) having a heterostructure raised source/drain region and method of making the same. A two layer raised source drain region (106) is located adjacent a gate structure (112). The first layer (106a) is a barrier layer comprising a first materia...	02/13/2001
6153454	Convex device with selectively doped channel In manufacturing a transistor, a doping mask is formed above a substrate. The doping mask is constructed, so that a first region of the substrate for serving as a source in the transistor and a second region of the substrate for serving as a drain in the ...	11/28/2000
6143593	Elevated channel MOSFET The present invention provides a method of producing a semiconductor device (e.g., a Metal Oxide Semiconductor Field Effect Transistor (MOSFET)) with a gate length less than 0.25 microns using standard process techniques arranged in an unstandardized proc...	11/07/2000
6124627	Lateral MOSFET having a barrier between the source/drain region and the channel region using a heterostructure raised source/drain region A MOSFET (100) having a heterostructure raised source/drain region and method of making the same. A two layer raised source drain region (106) is located adjacent a gate structure (112). The first layer (106a) is a barrier layer comprising a first materia...	09/26/2000
6124614	Si/SiGe MOSFET and method for fabricating the same The present invention relates to a metal silicon field effect transistor (MOSFET), and more particularly to a MOSFET, using a Si or SiGe channel to effectively adjust threshold voltage. The transistor according to the present invention can solve the probl...	09/26/2000

«First «Previous1 2 3 Next»Last»

PatentStorm

Bizarre Patents

PatentStorm News

Class 257/E21.409 - With an insulated gate (EPO)