Class 257/E21.403 - With heterojunction interface channel or gate, e.g., HFET, HIGFET, SISFET, HJFET, HEMT (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.4. This subclass
No. of patents: 27
Last issue date: 10/07/2008

Number	Title	Issue Date
7432538	Field-effect transistor A field-effect transistor includes a channel layer having a channel and a carrier supply layer, disposed on the channel layer, containing a semiconductor represented by the formula AlxGa1-xN, wherein x is greater than 0.04 and less than 0.45. T...	10/07/2008
7429534	Etching a nitride-based heterostructure An improved solution for producing nitride-based heterostructure(s), heterostructure device(s), integrated circuit(s) and/or Micro-Electro-Mechanical System(s) is provided. A nitride-based etch stop layer that includes Indium (In) is included in a heterostructure. A...	09/30/2008
7416929	Monolithic vertical junction field effect transistor and schottky barrier diode fabricated from silicon carbide and method for fabricating the same A switching element combining a self-aligned, vertical junction field effect transistor with etched-implanted gate and an integrated antiparallel Schottky barrier diode is described. The anode of the diode is connected to the source of the transistor at the device l...	08/26/2008
7417267	Non-planar III-nitride power device having a lateral conduction path A III-nitride power semiconductor device that includes a heterojunction body with a sloping portion, a first power electrode, a second power electrode and a gate over the sloping portion of the heterojunction to control the conduction of current between the first po...	08/26/2008
7408182	Surface passivation of GaN devices in epitaxial growth chamber The present invention relates to passivation of a gallium nitride (GaN) structure before the GaN structure is removed from an epitaxial growth chamber. The GaN structure includes one or more structural epitaxial layers deposited on a substrate, and the passivation l...	08/05/2008
7374988	NFET and PFET devices and methods of fabricating same A field effect transistor and method of fabricating the field effect transistor. The field effect transistor, including: a gate electrode formed on a top surface of a gate dielectric layer, the gate dielectric layer on a top surface of a single-crystal silicon chann...	05/20/2008
7291873	High electron mobility epitaxial substrate A compound semiconductor epitaxial substrate for use in a strain channel high electron mobility field effect transistor, comprising an InGaAs layer as a strain channel layer 6 and AlGaAs layers containing n-type impurities as back side and front side electron...	11/06/2007
7276747	Semiconductor device having screening electrode and method In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a screening electrode spaced apart from a channel region. ...	10/02/2007
7268362	High performance transistors with SiGe strain A preferred embodiment of the invention comprises a semiconductor device having stress in the source/drain channel. The device comprises a substrate having a lattice constant greater than or equal to silicon and a first layer on the substrate, wherein the first laye...	09/11/2007
7161179	Semiconductor device and method of manufacturing the same In a semiconductor device and a method of manufacturing the semiconductor device, the source wires 126 of a pixel portion 205 are formed of material having low resistance (representatively, aluminum, silver, copper). The source wires of a driving circu...	01/09/2007
7144765	Semiconductor device with Schottky electrode including lanthanum and boron, and manufacturing method thereof A semiconductor device and its manufacturing method. The semiconductor device has a semi-insulating GaAs substrate 310, a GaAs buffer layer 321 that is formed on the semi-insulating GaAs substrate 310, AlGaAs buffer layer 322, a channel l...	12/05/2006
6674100	SiGeC-based CMOSFET with separate heterojunctions Si and SiGeC layers are formed in an NMOS transistor on a Si substrate. A carrier accumulation layer is formed with the use of a discontinuous portion of a conduction band present at the heterointerface between the SiGeC and Si layers. Electrons travel in...	01/06/2004
6657223	Strained silicon MOSFET having silicon source/drain regions and method for its fabrication A strained silicon MOSFET utilizes a strained silicon layer formed on a silicon germanium layer. Strained silicon and silicon germanium are removed at opposing sides of the gate and are replaced by silicon regions. Deep source and drain regions are implan...	12/02/2003
6593191	Buried channel strained silicon FET using a supply layer created through ion implantation A method of fabricating a buried channel FET including providing a relaxed SiGe layer on a substrate, providing a channel layer on the relaxed SiGe layer, providing a SiGe cap layer on the channel layer, and ion implanting a dopant supply. The dopant supp...	07/15/2003
6555839	Buried channel strained silicon FET using a supply layer created through ion implantation A circuit including at least one strained channel, enhancement mode FET, and at least one strained channel, depletion mode FET. The depletion mode FET includes an ion implanted dopant supply. In exemplary embodiments, the FETs are surface channel or burie...	04/29/2003
6399970	FET having a Si/SiGeC heterojunction channel Si and SiGeC layers are formed in an NMOS transistor on a Si substrate. A carrier accumulation layer is formed with the use of a discontinuous portion of a conduction band present at the heterointerface between the SiGeC and Si layers. Electrons travel in...	06/04/2002
6306211	Method for growing semiconductor film and method for fabricating semiconductor device In a chamber, a substrate is mounted on a susceptor and then heated to an elevated temperature. Source and diluting gases are supplied into the chamber through source and diluting gas supply pipes provided with respective flow meters. In addition, a dopin...	10/23/2001
6225196	High electron mobility transistor and method of fabricating the same There is provided a field effect transistor including (a) an amorphous semiconductor layer made of amorphous silicon hydride containing impurities doped therein, (b) a semiconductor layer made of single crystal silicon having electron affinity greater tha...	05/01/2001
6190975	Method of forming HCMOS devices with a silicon-germanium-carbon compound semiconductor layer Si and SiGeC layers are formed in an NMOS transistor on a Si substrate. A carrier accumulation layer is formed with the use of a discontinuous portion of a conduction band present at the heterointerface between the SiGeC and Si layers. Electrons travel in...	02/20/2001
6117713	Method of producing a MESFET semiconductor device having a recessed gate structure An insulating layer is formed on a semiconductor substrate, and a first resist layer having a first resist opening portion is formed on the insulating layer. Then, the insulating layer is etched thought the opening portion to expose the substrate. After r...	09/12/2000
6049091	High electron mobility transistor There is provided a field effect transistor including (a) an amorphous semiconductor layer made of amorphous silicon hydride containing impurities doped therein, (b) a semiconductor layer made of single crystal silicon having an electron affinity greater ...	04/11/2000
6004137	Method of making graded channel effect transistor A MISFET having a graded semiconductor alloy channel layer of silicon germanium in which the germanium is graded to a single peak percentage level. The single peak percentage level defines the location of the charge carriers within the layer. The transcon...	12/21/1999
5821577	Graded channel field effect transistor A MISFET having a graded semiconductor alloy channel layer of silicon germanium in which the germanium is graded to a single peak percentage level. The single peak percentage level defines the location of the charge carriers within the layer. The transcon...	10/13/1998
5442205	Semiconductor heterostructure devices with strained semiconductor layers A heterostructure includes a stained epitaxial layer of either silicon or germanium that is located overlying a silicon substrate, with a spatially graded Gex Si1-x epitaxial layer overlain by a ungraded Gex.sbsb.0 Si...	08/15/1995
5285088	High electron mobility transistor A semiconductor device capable of reducing element sizes exceedingly and a mask alignment accuracy in lithography is provided. This device has a pair of semiconductor layers for source/drain electrodes formed on the field insulating film so as to be respe...	02/08/1994
5274255	Structure for providing high resolution modulation of voltage potential in the vicinity of a surface A structure for modulating electrostatic potential in the vicinity of a surface of a structure comprises: a substrate; a first electrically conductive layer having an exposed surface and made of a first electrically conducive material formed on the subrat...	12/28/1993
5221413	Method for making low defect density semiconductor heterostructure and devices made thereby The present invention is predicated upon the discovery by applicants that by growing germanium-silicon alloy at high temperatures in excess of about 850° C. and increasing the germanium content at a gradient of less than about 25% per micrometer, one can...	06/22/1993

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Class 257/E21.403 - With heterojunction interface channel or gate, e.g., HFET, HIGFET, SISFET, HJFET, HEMT (EPO)