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| Number | Title | Issue Date |
| 7435628 | Method of forming a vertical MOS transistor A vertical MOS transistor has a source region, a channel region, and a drain region that are vertically stacked, and a trench that extends from the top surface of the drain region through the drain region, the channel region, and partially into the source region. Th... | 10/14/2008 |
| 7436017 | Semiconductor integrated circuit using a selective disposable spacer Methods of manufacturing a semiconductor integrated circuit using selective disposable spacer technology and semiconductor integrated circuits manufactured thereby: The method includes forming a plurality of gate patterns on a semiconductor substrate. Gap regions be... | 10/14/2008 |
| 7388255 | Semiconductor device having separation region A semiconductor device includes: a semiconductor substrate; a separation region in the substrate; an embedded layer; a channel forming region; a source region; a drain region; a first electrode for the source region; a second electrode for the channel forming region... | 06/17/2008 |
| 7361557 | Insulated gate type semiconductor device and method for fabricating the same In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a por... | 04/22/2008 |
| 7335555 | Buried-contact solar cells with self-doping contacts A buried-contact solar cell, in-process buried-contact solar cell components and methods for making buried contact solar cells wherein a self-doping contact material is placed in a plurality of buried-contact surface grooves. By combining groove doping and metalliza... | 02/26/2008 |
| 7271068 | Method of manufacture of semiconductor device A power MISFET, which has a desired gate breakdown voltage, can be manufactured will controlling an increase in parasitic capacitance. After depositing a polycrystalline silicon film on a substrate and embedding groove portions in the polycrystalline silicon film by... | 09/18/2007 |
| 7250345 | Insulated gate transistor A semiconductor device of the present invention is provided with a power device which has a semiconductor substrate having a first main surface and a second main surface that are opposed to each other and an insulating gate structure on the first main surface side, ... | 07/31/2007 |
| 7199019 | Method for forming tungsten contact plug A method for forming a tungsten contact plug of a semiconductor device including depositing an insulating layer on a semiconductor substrate, etching the insulating layer to form a contact hole, which exposes a conductive region, forming a barrier layer on the semic... | 04/03/2007 |
| 7189621 | Semiconductor device and method for fabricating the same Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of ... | 03/13/2007 |
| 7189617 | Manufacturing method for a recessed channel array transistor and corresponding recessed channel array transistor The present invention relates to a manufacturing method for a recessed channel array transistor and a corresponding recessed channel array transistor. In one embodiment, the present invention uses a self-adjusting spacer on the substrate surface to provide the requi... | 03/13/2007 |
| 6696323 | Method of manufacturing semiconductor device having trench filled up with gate electrode In a semiconductor device, a p-type base region is provided in an n- -type substrate to extend from a principal surface of the substrate in a perpendicular direction to the principal surface. An n+ -type source region extends in the ... | 02/24/2004 |
| 6683343 | High voltage semiconductor device having two buffer layer In an IGBT, an n buffer layer is formed under an n- high resistance layer in which a MOS gate structure is formed. An n+ buffer layer is formed between the n buffer layer and a p+ drain layer. Since the p+ drain... | 01/27/2004 |
| 6673681 | Process for forming MOS-gated power device having segmented trench and extended doping zone A process for constructing a trench MOS-gated device includes: forming in a semiconductor substrate an extended trench that comprises an upper segment and a bottom segment, wherein the bottom segment has a lesser width relative to a greater width of the t... | 01/06/2004 |
| 6670658 | Power semiconductor element capable of improving short circuit withstand capability while maintaining low on-voltage and method of fabricating the same In a p-type base layer of a trench IGBT comprising a p-type collector layer, an n-type base layer formed on the p-type collector layer, the p-type base layer formed on the n-type base layer, and an n-type emitter layer formed on the surface of the p-type ... | 12/30/2003 |
| 6670244 | Method for fabricating a body region for a vertical MOS transistor arrangement having a reduced on resistivity A method is provided for fabricating a body region of a first conduction type for a vertical MOS transistor configuration in a semiconductor body such that the body region has a reduced resistivity without a corresponding reduction in the breakdown voltag... | 12/30/2003 |
| 6660591 | Trench-gate semiconductor devices having a channel-accommodating region and their methods of manufacture Compact trench-gate semiconductor devices, for example a cellular power MOSFET with sub-micron pitch (Yc), are manufactured with self-aligned techniques that use sidewall spacers (52) in different ways. Thereby, the source region (13) and a contact window... | 12/09/2003 |
| 6661054 | Semiconductor device and method of fabricating the same A gate electrode is provided to fill up a trench while covering its opening. Assuming that WG represents the diameter (sectional width) of a head portion of the gate electrode located upward beyond a P-type base layer and an... | 12/09/2003 |
| 6642600 | Insulated gate semiconductor device having first trench and second trench connected to the same A second trench (105b) is formed inside a semiconductor layer (102), penetrating a base layer (103) and moreover extends along a second direction (D2) while being connected to one end portion of each first portion (P1) of a first trench (105a) extending a... | 11/04/2003 |
| 6638826 | Power MOS device with buried gate An MOS power device a substrate comprises an upper layer having an upper surface and an underlying drain region, a well region of a first conductance type disposed in the upper layer over the drain region, and a plurality of spaced apart buried gates, eac... | 10/28/2003 |
| 6630711 | Semiconductor structures with trench contacts Semiconductor structures such as the trench and planar MOSFETs (UMOS), trench and planar IGBTs and trench MCTs using trenches to establish a conductor. Improved control of the parasitic transistor in the trench MOSFET is also achieved and cell size and pi... | 10/07/2003 |
| 6630389 | Method for manufacturing semiconductor device In a trench-gate type power MOSFET in which a gate electrode is formed on a gate oxide layer formed on a surface of a wall defining a trench, the trench is annealed by heating, for example, at the temperature between 1050° C. and 1150° C. in a hydrogen ... | 10/07/2003 |
| 6620669 | Manufacture of trench-gate semiconductor devices A vertical power transistor trench-gate semiconductor device has an active area (100) accommodating transistor cells and an inactive area (200) accommodating a gate electrode (25) (FIG. 6). While an n-type layer (14) suitable for drain regions still exten... | 09/16/2003 |
| 6610572 | Semiconductor device and method for manufacturing the same A semiconductor device is provided which can be manufactured even by using an inexpensive FZ wafer in a wafer process and still has a sharp inclination of a high impurity concentration in a high impurity concentration layer at the outermost portion of the... | 08/26/2003 |
| 6605858 | Semiconductor power device A p type base layer is formed in one surface region of an n type base layer. An n type emitter layer is formed in a surface region of the p type base layer. An emitter electrode is formed on the n type emitter layer and the p type base layer. A trench is ... | 08/12/2003 |
| 6566691 | Semiconductor device with trench gate having structure to promote conductivity modulation An IGBT has a p-emitter layer and p-base layer, which are arranged on both sides of an n-base layer. A pair of main trenches are formed to extend through the p-base layer and reach the n-base layer. In a current path region interposed between the main tre... | 05/20/2003 |
| 6541818 | Field-effect transistor configuration with a trench-shaped gate electrode and an additional highly doped layer in the body region A field effect transistor configuration with a trench gate electrode and a method for producing the same. An additional highly doped layer is provided in the body region under the source. The layer is used for influencing the conductibility of the source ... | 04/01/2003 |
| 6538280 | Trenched semiconductor device and method of fabricating the same In a trenched MOS gate power device having a trenched MOS gate structure, a gate insulating film is formed on the walls of trenches to extend onto a major surface of a semiconductor substrate, and gates are formed so as to fill up the trenches and to exte... | 03/25/2003 |
| 6534367 | Trench-gate semiconductor devices and their manufacture Compact trench-gate semiconductor devices, for example a cellular power MOSFET with sub-micron pitch (Yc), are manufactured with self-aligned techniques that use sidewall spacers (52) in different ways. The trench-gate (11) is accommodated in a narrow tre... | 03/18/2003 |
| 6525375 | Semiconductor device having trench filled up with gate electrode In a semiconductor device, a p-type base region is provided in an n- -type substrate to extend from a principal surface of the substrate in a perpendicular direction to the principal surface. An n+ -type source region extends in the ... | 02/25/2003 |
| 6525373 | Power semiconductor device having trench gate structure and method for manufacturing the same A power semiconductor device having a trench gate structure in which it is possible to reduce the number of required masks and to improve its characteristics, and a method for manufacturing the same, includes a semiconductor substrate and a semiconductor ... | 02/25/2003 |
| 6521498 | Manufacture or trench-gate semiconductor devices The manufacture of a vertical power transistor trench-gate semiconductor device in which the source regions (13) are self-aligned to the trench-gate structures (20,17,11) including the steps of forming a mask (61) on a surface (10a) of a semiconductor bod... | 02/18/2003 |
| 6521538 | Method of forming a trench with a rounded bottom in a semiconductor device In a method for manufacturing a semiconductor device, first, a trench is formed on a semiconductor substrate by anisotropic etching, and a reaction product is produced and deposited on the inner wall of the trench during the anisotropic etching. Then, iso... | 02/18/2003 |
| 6518624 | Trench-gate power semiconductor device preventing latch-up and method for fabricating the same A trench-gate power semiconductor device and a method for fabricating the same are provided. The trench-gate power semiconductor device includes a semiconductor substrate of a first conductivity type used as a collector region, a buffer layer of a second ... | 02/11/2003 |
| 6518129 | Manufacture of trench-gate semiconductor devices The manufacture of a trench-gate semiconductor device, for example a power transistor or a memory device includes the steps of forming at a surface (10a) of a semiconductor body (10) a first mask (51) having a first window (51a), providing a thin layer of... | 02/11/2003 |
| 6498071 | Manufacture of trench-gate semiconductor devices In the manufacture of a trench-gate semiconductor device, for example a MOSFET or an IGBT, a starting semiconductor body (10) has two top layers (13, 15) provided for forming the source and body regions. Gate material (11') is provided in a trench (20) wi... | 12/24/2002 |
| 6495871 | Power semiconductor element capable of improving short circuit withstand capability while maintaining low on-voltage and method of fabricating the same In a p-type base layer of a trench IGBT comprising a p-type collector layer, an n-type base layer formed on the p-type collector layer, the p-type base layer formed on the n-type base layer, and an n-type emitter layer formed on the surface of the p-type ... | 12/17/2002 |
| 6482701 | Integrated gate bipolar transistor and method of manufacturing the same A method of manufacturing a trench gate type IGBT element, which can sufficiently round off a corner at a bottom of a trench with restricting silicon from being excessively etched. A trench is formed at a surface of a P+ -type monocrystalline s... | 11/19/2002 |
| 6469345 | Semiconductor device and method for manufacturing the same A trench-gate type transistor has a gate insulating film formed on an inner wall of a trench. The gate insulating film is composed of a first portion disposed on a side wall portion of the trench and a second portion disposed on upper and bottom portions ... | 10/22/2002 |
| 6455379 | Power trench transistor device source region formation using silicon spacer A power trench MOS-gated transistor is constructed with a buried gate to source dielectric inside a gate trench region. In the innovative device, a thick oxide (grown or deposited) is used to define the height of the trench walls. A body region is initial... | 09/24/2002 |
| 6448139 | Manufacturing method of semiconductor device A semiconductor substrate has a trench for forming a gate insulation film and a gate electrode therein, or an insulated isolation isolating a semiconductor element like a transistor from other elements. The trench is formed by anisotropic dry etching. Aft... | 09/10/2002 |
