Class 257/E21.377 - Mesa-planar transistor (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.375. This
No. of patents: 4
Last issue date: 10/30/2007

Number	Title	Issue Date
7288446	Single and double-gate pseudo-FET devices for semiconductor materials evaluation Several methods and structures are disclosed for determining electrical properties of silicon-on-insulator (SOI) wafers and alternate versions of such wafers such as strained silicon:silicon/germanium:-on-insulator (SSGOI) wafers. The analyzed electrical properties ...	10/30/2007
7265059	Multiple fin formation A FinFET includes a plurality of semiconductor fins. Over a semiconductor layer, patterned features (e.g. of minimum photolithographic size and spacing) are formed. In one example of fin formation, a first set of sidewall spacers are formed adjacent to the sides of ...	09/04/2007
7145220	Fin semiconductor device and method for fabricating the same A semiconductor device includes second to fourth semiconductor layers, a gate electrode, and an insulating film. The second semiconductor layer is formed on a first semiconductor layer and has a projecting shape. The third and fourth semiconductor layers are formed ...	12/05/2006
4431460	Method of producing shallow, narrow base bipolar transistor structures via dual implantations of selected polycrystalline layer A method for fabricating high performance NPN bipolar transistors which result in shallow, narrow base devices is described. The method includes depositing a polycrystalline silicon layer over a monocrystalline silicon surface in which the base and emitte...	02/14/1984

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