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| Number | Title | Issue Date |
| 7439572 | Stacked gate memory cell with erase to gate, array, and method of manufacturing A stacked gate nonvolatile memory floating gate device has a control gate. Programming of the cell in the array is accomplished by hot channel electron injecton from the drain to the floating gate. Erasure occurs by Fowler-Nordheim tunneling of electrons from the fl... | 10/21/2008 |
| 7439137 | Method for manufacturing semiconductor device In a MOSFET, after an element region is formed, a wiring layer is formed subsequently to a barrier metal layer, and hydrogen annealing is performed. However, in the case of an n-channel MOSFET, a threshold voltage is lowered due to an occlusion characteristic of the... | 10/21/2008 |
| 7439558 | Method and system for controlled oxygen incorporation in compound semiconductor films for device performance enhancement A method and system for providing a bipolar transistor is described. The method and system include providing a compound base region, providing an emitter region coupled with the compound base region, and providing a collector region coupled with the compound base re... | 10/21/2008 |
| 7414298 | Super self-aligned collector device for mono-and hetero bipolar junction transistors, and method of making same The invention relates to a process of forming a compact bipolar junction transistor (BJT) that includes forming a self-aligned collector tap adjacent the emitter stack and an isolation structure. A base layer is formed from epitaxial silicon that is disposed in the ... | 08/19/2008 |
| 7410856 | Methods of forming vertical transistors A vertical transistor forming method includes forming a first pillar above a first source/drain and between second and third pillars, providing a first recess between the first and second pillars and a wider second recess between the first and third pillars, forming... | 08/12/2008 |
| 7364997 | Methods of forming integrated circuitry and methods of forming local interconnects In one implementation, field oxide is grown within bulk semiconductive material in a first circuitry area and not over immediately adjacent bulk semiconductive material in a second circuitry area. The field oxide is etched from the first circuitry area. After the et... | 04/29/2008 |
| 7347228 | Method of making semiconductor devices A method for fabricating semiconductor device is provided. A high stress layer formed on, under or on both sides of the transistors of the semiconductor device is employed as a cap layer. A specific region is then defined through photo resistor mask, and the stress ... | 03/25/2008 |
| 7288815 | Semiconductor device and manufacturing method thereof A semiconductor device (20, 21, 22), including: a channel region (4) of a first conductivity type formed at a surface layer portion of a semiconductor substrate (1); a source region (25) of a second conductivity type which is different fr... | 10/30/2007 |
| 7276754 | Annular gate and technique for fabricating an annular gate A memory structure having a vertically oriented access transistor with an annular gate region and a method for fabricating the structure. More specifically, a transistor is fabricated such that the channel of the transistor extends outward with respect to the surfac... | 10/02/2007 |
| 7271048 | Method for manufacturing trench MOSFET A method of manufacturing a trench MOSFET with high cell density is disclosed. The method introduces a sidewall oxide spacer for narrowing the opening of the trench structure, thereby decreasing the cell pitch of the memory units. Moreover, the source structure is f... | 09/18/2007 |
| 7271067 | Voltage sustaining layer with opposite-doped islands for semiconductor power devices A semiconductor high-voltage device comprising a voltage sustaining layer between a n+-region and a p+-region is provided, which is a uniformly doped n (or p)-layer containing a plurality of floating p (or n)-islands. The effect of the floating islands is to absorb ... | 09/18/2007 |
| 7259048 | Vertical replacement-gate silicon-on-insulator transistor An architecture for creating a vertical silicon-on-insulator MOSFET. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain contact region formed in the surface. A relatively thin s... | 08/21/2007 |
| 7253070 | Transistor structure with minimized parasitics and method of fabricating the same A transistor having minimized parasitics is provided including an emitter having a recessed extrinsic emitter portion atop an intrinsic emitter portion; a base including an intrinsic base portion in electrical contact with the intrinsic emitter portion and an extrin... | 08/07/2007 |
| 7208370 | Method for fabricating a vertical transistor in a trench, and vertical transistor To fabricate a vertical transistor, a trench is provided, the side wall of which is formed by a semiconductor substrate in single crystal form and the base of which is formed by a polycrystalline semiconductor substrate. A transition region is arranged between the s... | 04/24/2007 |
| 6703686 | Semiconductor device An n-type low impurity concentration semiconductor layer is provided, by epitaxial growth or the like, on a p-type semiconductor substrate. In order to vertically form a semiconductor device in the low impurity concentration semiconductor layer, at least ... | 03/09/2004 |
| 6703685 | Super self-aligned collector device for mono-and hetero bipolar junction transistors The invention relates to a process of forming a compact bipolar junction transistor (BJT) that includes forming a self-aligned collector tap adjacent the emitter stack and an isolation structure. A base layer is formed from epitaxial silicon that is dispo... | 03/09/2004 |
| 6703283 | Discontinuous dielectric interface for bipolar transistors A process for forming at least one interface region between two regions of semiconductor material. At least one region of dielectric material comprising nitrogen is formed in the vicinity of at least a portion of a boundary between the two regions of semi... | 03/09/2004 |
| 6692982 | Optical semiconductor integrated circuit device and manufacturing method for the same In an optical semiconductor integrated circuit device in which a vertical pnp transistor and a photodiode are formed, the preferred embodiments of the present invention eliminates difficulty in performance improvement of the two elements. In an illustrati... | 02/17/2004 |
| 6686251 | Method for fabricating a bipolar transistor having self-aligned emitter and base A method for forming a self-aligned bipolar transistor includes the steps of combination etching a silicon substrate in an opening to form a concave surface on the silicon substrate, and forming an intrinsic base and an associated emitter on the concave s... | 02/03/2004 |
| 6673703 | Method of fabricating an integrated circuit A method of fabricating an integrated circuit including a monocrystalline silicon substrate, a layer of polycrystalline silicon on the top surface of the substrate and doped with at least two dopants with different rates of diffusion, in which method anne... | 01/06/2004 |
| 6660570 | Method of fabricating a high voltage semiconductor device using SIPOS A high voltage semiconductor device including a semiconductor substrate on which a semi-insulating polycrystalline silicon layer is formed to alleviate electric field concentration in a field region, is disclosed. A thermal oxide layer is formed on the se... | 12/09/2003 |
| 6657242 | Trench-isolated bipolar devices In order to produce an electrical connection to an inner layer such as a bottom diffusion (103), which has a good electrical conductivity and is located inside a bipolar semiconductor device isolated by trenches (119) and which for example forms a subcoll... | 12/02/2003 |
| 6657281 | Bipolar transistor with a low K material in emitter base spacer regions The present invention provides a bipolar transistor located on a semiconductor wafer substrate. The bipolar transistor may comprise a collector located in the semiconductor wafer substrate, a base located in the collector, and an emitter located on the ba... | 12/02/2003 |
| 6656811 | Carbide emitter mask etch stop Bipolar transistors and methods for fabricating bipolar transistors are disclosed wherein an emitter-base dielectric stack is formed between emitter and base structures, comprising a carbide layer situated between first and second oxide layers. The carbid... | 12/02/2003 |
| 6649983 | Vertical bipolar transistor formed using CMOS processes A vertical bipolar transistor is described which utilizes ion implantation steps which are used to form an nMOS field effect device and a pMOS field effect device. The implantation steps form an n-well, a p-well region, a pocket base region and an emitter... | 11/18/2003 |
| 6646320 | Method of forming contact to poly-filled trench isolation region Existing polysilicon emitter technology is used to contact poly fill in a trench isolation structure. A standard single poly emitter window process is followed. An "emitter window" is masked directly over the polysilicon trench fill. Heavily doped single ... | 11/11/2003 |
| 6642121 | Control of amount and uniformity of oxidation at the interface of an emitter region of a monocrystalline silicon wafer and a polysilicon layer formed by chemical vapor deposition A method of controlling the quantity and uniformity of distribution of bonded oxygen atoms at the interface between the polysilicon and the monocrystalline silicon includes carrying out, after having loaded the wafer inside the heated chamber of the react... | 11/04/2003 |
| 6642096 | Bipolar transistor manufacturing A method of manufacturing a bipolar transistor in a single-crystal silicon substrate of a first conductivity type, including a step of carbon implantation at the substrate surface followed by an anneal step, before forming, by epitaxy, the transistor base... | 11/04/2003 |
| 6630377 | Method for making high-gain vertical bipolar junction transistor structures compatible with CMOS process An improved NPN bipolar transistor integratable with CMOS FET processing is achieved. The transistor is formed on a substrate using a CMOS process and one additional masking and implant step. The CMOS N wells are used to form the collector contacts (reach... | 10/07/2003 |
| 6624497 | Semiconductor device with a reduced mask count buried layer An N type buried layer is formed, in one embodiment, by a non selective implant on the surface of a wafer and later diffusion. Subsequently, the wafer is masked and a selective P type buried layer is formed by implant and diffusion. The coefficient of dif... | 09/23/2003 |
| 6607961 | Method of definition of two self-aligned areas at the upper surface of a substrate A method for defining, on the upper surface of a substrate, two self-aligned areas, including the steps of depositing a protective layer; depositing a covering layer; opening the protective and covering layers at a location substantially corresponding to ... | 08/19/2003 |
| 6602755 | Method for manufacturing a compact bipolar transistor structure A bipolar transistor structure that includes a semiconductor material substrate that has a bottom substrate and base region of a first conductivity type and a buried layer, collector region and sink region of a second conductivity type. The substrate has ... | 08/05/2003 |
| 6600211 | Bipolar transistor constructions The invention includes a bipolar transistor construction having a collector region, emitter region, and base region extending within a semiconductive material substrate. The construction further comprises separate access regions associated with the base r... | 07/29/2003 |
| 6590273 | Semiconductor integrated circuit device and manufacturing method thereof In the semiconductor integrated circuit device, a first P+ type buried layer formed as an anode region and an N+ type diffused region formed in a cathode region are spaced from each other in the direction of the depth. This makes it ... | 07/08/2003 |
| 6569744 | Method of converting a metal oxide semiconductor transistor into a bipolar transistor The present invention provides a method of manufacturing a bipolar transistor. The method includes producing an opening in a dielectric layer located over a substrate and forming a collector in the substrate by implanting a first dopant through the openin... | 05/27/2003 |
| 6569730 | High voltage transistor using P+ buried layer A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This... | 05/27/2003 |
| 6551890 | Method of manufacturing a semiconductor device comprising a bipolar transistor and a capacitor A method of manufacturing a semiconductor device comprising a poly-emitter transistor (1) and a capacitor (2). A base electrode (14), a first electrode (16, 37) and an emitter window (18) are formed at the same time in a first polysilicon layer (13) cover... | 04/22/2003 |
| 6551891 | Process for fabricating a self-aligned vertical bipolar transistor The fabrication process comprises a phase of producing a base region having an extrinsic base and an intrinsic base, and a phase of producing an emitter region comprising an emitter block having a narrower lower part located in an emitter window provided ... | 04/22/2003 |
| 6548337 | Method of manufacturing a high gain bipolar junction transistor with counterdoped base in CMOS technology A method is described for forming a high gain bipolar junction transistor in a optimized CMOS integrated circuit. The bipolar junction transistor comprises a compensated base region (130) which is formed by forming the p-well region (20) and the n-well re... | 04/15/2003 |
| 6538294 | Trenched semiconductor device with high breakdown voltage An arrangement in a semiconductor component includes a highly doped layer on a substrate layer and is delimited by at least one trench extending from the surface of the component through the highly doped layer. A sub-layer between the substrate layer and ... | 03/25/2003 |
