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| Number | Title | Issue Date |
| 7442616 | Method of manufacturing a bipolar transistor and bipolar transistor thereof A bipolar transistor (100) is manufactured using the following processes: (a) forming a base electrode layer (129) as a portion of a base electrode over a semiconductor substrate (110); (b) forming a first portion of an emitter electrode (154... | 10/28/2008 |
| 7439135 | Self-aligned body contact for a semiconductor-on-insulator trench device and method of fabricating same A structure and method of forming a body contact for an semiconductor-on-insulator trench device. The method including: forming set of mandrels on a top surface of a substrate, each mandrel of the set of mandrels arranged on a different corner of a polygon and exten... | 10/21/2008 |
| 7422916 | Method of manufacturing thin film transistor panel A method of manufacturing a thin film transistor panel is provided, which includes forming a first signal line on a substrate. The method also includes forming in sequence a first insulating layer and a semiconductor layer on the first signal line. The method furthe... | 09/09/2008 |
| 7397108 | Bipolar transistor A monolithically integrated bipolar transistor has an SOI substrate, a collector region in the SOI substrate, a base layer region on top of and in contact with the collector region, and an emitter layer region on top of and in contact with the base layer region, whe... | 07/08/2008 |
| 7382021 | Insulated gate field-effect transistor having III-VI source/drain layer(s) A transistor includes one or more channel taps containing a stack consisting at least in part of a semiconductor an interfacial III-VI layered compound and a conductor. The III-VI compound consists primarily of atoms from Groups IIIA-B and from Group VIA of the Peri... | 06/03/2008 |
| 7351615 | Method of fabricating a MIS transistor A method of fabricating MIS transistors starts with formation of gate electrode portions. Then, high-speed ions are irradiated through an insulating film to implant impurity ions into a semiconductor region by a self-aligning process, followed by total removal of th... | 04/01/2008 |
| 7316942 | Flexible active matrix display backplane and method An active matrix display backplane is formed by annealing a flexible dielectric substrate, and then forming one or more thin-film-transistors (TFTs), one or more pixel electrodes, and an interconnect on a surface of the annealed substrate. The interconnect includes ... | 01/08/2008 |
| 7297992 | Method and structure for integration of phosphorous emitter in an NPN device in a BiCMOS process According to one exemplary embodiment, a heterojunction bipolar transistor includes a base situated on a substrate. The heterojunction bipolar transistor can be an NPN silicon-germanium heterojunction bipolar transistor, for example. The heterojunction bipolar trans... | 11/20/2007 |
| 7285457 | Heterojunction bipolar transistor and manufacturing method thereof In the method for manufacturing a heterojunction bipolar transistor, a collector contact layer, a collector layer, a base layer, a base protection layer, an emitter layer, an emitter contact layer, and a WSi layer are sequentially formed on a substrate. A resist pat... | 10/23/2007 |
| 7259047 | Method for manufacturing organic thin-film transistor with plastic substrate A method for manufacturing an organic thin-film transistor with a plastic substrate, comprising steps of: providing a mold and a plastic substrate, said mold being provided with a relief printing structure; imprinting said plastic substrate by said mold so as to def... | 08/21/2007 |
| 7148090 | Method of fabricating a TFT device formed by printing A thin-film transistor for an active matrix display is fabricated using printing means, such as a gravure offset printer. First and second pattern layers (251, 252; 30) are formed on a layer structure (4) wherein at ... | 12/12/2006 |
| 6680232 | Trench etch with incremental oxygen flow A method for forming trenches in a device layer disposed on a silicon semiconductor substrate comprises: covering the device layer with an etch resistant masking layer to define at least two trench regions; removing semiconductor material from the exposed... | 01/20/2004 |
| 6570240 | Semiconductor device having a lateral bipolar transistor and method of manufacturing same In order to form a semiconductor device including a lateral bipolar transistor which is a match in the device performance for a vertical bipolar transistor, an electrically conductive film which is formed by filling a trench reaching a buried oxide film i... | 05/27/2003 |
| 6500721 | Bipolar thin-film transistors and method for forming A bipolar junction transistor includes a substrate, a first layer, a second layer, and a third layer. The first layer comprises non-single-crystalline semiconductor material having a first conductivity type deposited on the substrate. The second layer com... | 12/31/2002 |
| 6376880 | High-speed lateral bipolar device in SOI process A lateral bipolar transistor includes a semiconductor layer overlying an electrically insulating material and an insulating layer overlying a central portion of the semiconductor layer. A contact hole resides in the insulating layer and a conductive mater... | 04/23/2002 |
| 6326292 | Semiconductor component and manufacturing method for semiconductor component A semiconductor includes a buried conducting layer, such as a buried collector, comprises a trench, the walls of which are covered with a layer of a material in which dopant ions diffuse faster than in monocrystalline silicon. A contact area is doped in c... | 12/04/2001 |
| 6323538 | Bipolar transistor and method for fabricating the same An n-type first single crystal silicon layer is provided as collector region over a silicon substrate with a first insulating film interposed therebetween. A p-type first polysilicon layer is provided as an extension of a base region over the first single... | 11/27/2001 |
| 6300220 | Process for fabricating isolation structure for IC featuring grown and buried field oxide An isolation structure having both deep and shallow components is formed in a semiconductor workpiece by etching the workpiece to define raised precursor active device regions separated by sunken precursor isolation regions. An oxidation mask is formed to... | 10/09/2001 |
| 6246104 | Semiconductor device and method for manufacturing the same An Si semiconductor device has an emitter region, a base region and a collector region formed on a substrate substantially in parallel to a plane of the substrate. And at least one of the emitter region the base region and the collector region includes an... | 06/12/2001 |
| 6235601 | Method of manufacturing a self-aligned vertical bipolar transistor A process is set forth for providing a self-aligned, vertical bipolar transistor. A controlled technique is provided for providing the base and emitter features of the transistor with appropriate dimensions and properties to be useful in high frequency mi... | 05/22/2001 |
| 6232649 | Bipolar silicon-on-insulator structure and process A process for fabricating a bipolar transistor on a silicon-on-insulator substrate which includes etching a bipolar transistor area into the substrate, wherein the bipolar transistor area has substantially vertical sidewalls and a bottom, and forming a bu... | 05/15/2001 |
| 6174779 | Method for manufacturing a lateral bipolar transistor In a lateral bipolar transistor, its emitter region, base region, link base region, and so forth, are made in self alignment with side walls of masks by using partly overlapping two mask patterns. Therefore, not relying on the mask alignment accuracy, the... | 01/16/2001 |
| 6140195 | Method for fabricating a lateral collector structure on a buried oxide layer The present invention provides a collector device in a bipolar device, having a lateral collector structure on a buried oxide layer. This collector has a high breakdown voltage for high power and operating at a high speed, by isolating a horizontal collec... | 10/31/2000 |
| 6001711 | Process of fabricating semiconductor device having gettering site layer between insulating layer and active semiconductor layer Phosphorous ion is implanted into an SOI substrate under the conditions that the concentration is maximized in the upper silicon layer of the SOI substrate so as to forming a heavily-doped damaged layer, and the heavily-doped damaged layer is partially cu... | 12/14/1999 |
| 5936278 | Semiconductor on silicon (SOI) transistor with a halo implant A semiconductor over insulator transistor (100) includes a semiconductor mesa (36) formed over an insulating layer (34) which overlies a semiconductor substrate (32). Source and drain regions (66, 68) of a first conductivity type are formed at opposite en... | 08/10/1999 |
| 5920108 | Late process method and apparatus for trench isolation Trenches 72 are formed in substrate 17 late in the fabrication process. In order to avoid trench sidewall stresses that cause defects in the substrate monocrystalline lattice, the trenches are filled after a final thick thermal oxide layer, such as a LOCO... | 07/06/1999 |
| 5856700 | Semiconductor device with doped semiconductor and dielectric trench sidewall layers The present invention is directed to a semiconductor device having an ohmic contact to a buried layer. The device includes a device wafer having on its first surface a first dielectric layer and on its second surface a doped epitaxial layer that comprises... | 01/05/1999 |
| 5851858 | Method for producing a multiplicity of microelectronic circuits on SOI A method for producing a multiplicity of microelectronic circuits on SOI produces n-CMOS or p-CMOS transistors, NPN transistors or PNP transistors, for instance, through the use of a standardized process, in an especially simple way. All that is required ... | 12/22/1998 |
| 5846858 | SOI-BiCMOS method In a manufacturing method for lateral bipolar transistors on an SOI substrate, a ridge-shaped gate electrode (8/9) is applied onto a mesa (3) provided with a basic doping and is covered surface-wide with a TEOS layer (10) that has vertical portions functi... | 12/08/1998 |
| 5763931 | Semiconductor device with SOI structure and fabrication method thereof A semiconductor device having the SOI structure is provided, which enables to reduce the size of components compared with the conventional semiconductor devices. The device contains a first insulator film formed on a semiconductor substrate, and semicondu... | 06/09/1998 |
| 5728613 | Method of using an insulator spacer to form a narrow base width lateral bipolar junction transistor A process has been developed in which narrow base width, lateral bipolar junction transistors, and narrow channel length MOSFET devices, can be simultaneously fabricated, in a silicon on insulator layer. The narrow base width is defined by the width of an... | 03/17/1998 |
| 5723370 | FET and/or bipolar devices formed in thin vertical silicon on insulator (SOI) structures A process for fabricating Ultra Large Scale Integrated (ULSI) circuits in Silicon On Insulator (SOI) technology in which the device structures, which can be bipolar, FET, or a combination, are formed in vertical silicon sidewalls having insulation under a... | 03/03/1998 |
| 5714397 | Process for producing lateral bipolar transistor In a lateral bipolar transistor and a method for producing the same, an emitter layer and a collector layer are disposed on a structured dielectric layer. The structured dielectric layer is located in a plane of a base layer and is interrupted by the base... | 02/03/1998 |
| 5705839 | Gate spacer to control the base width of a lateral bipolar junction transistor using SOI technology A process has been developed in which narrow base width, lateral bipolar junction transistors, and narrow channel length MOSFET devices, can be simultaneously fabricated, using a silicon on insulator approach. Insulator sidewall spacer and gate processing... | 01/06/1998 |
| 5663078 | Method for fabricating transistors using crystalline silicon devices on glass A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the ... | 09/02/1997 |
| 5637513 | Fabrication method of semiconductor device with SOI structure A fabrication method of a semiconductor device that can realize a semiconductor device having an improved radiation performance of heat together with a low parasitic capacitance between a semiconductor substrate and a conductor of the device. An SOI struc... | 06/10/1997 |
| 5637909 | Semiconductor device and method of manufacturing the same A bipolar transistor is formed on a silicon substrate having a silicon oxide film. An n-silicon layer having a top surface of a (100) plane is formed on the silicon oxide film and is used as a collector layer. An end face constituted by a (111) plane is f... | 06/10/1997 |
| 5635411 | Method of making semiconductor apparatus One NPN or PNP transistor is formed on a Si single crystal island having a crystal orientation which is the same as that of a Si substrate and formed into an island shape through an insulation and separation layer on the Si substrate so as to form a semic... | 06/03/1997 |
| 5633190 | Semiconductor device and method for making the same Disclosed is a semiconductor device in which dummy regions which are lower than an isolated element region are formed around the isolated element region. Another dummy region which has a height nearly equal to those of element regions may be formed at a n... | 05/27/1997 |
| 5629217 | Method and apparatus for SOI transistor A lateral bipolar transistor capable of forming a narrow-sized diffusion region, such as a base width, is disclosed. The transistor exhibits no scattering in the direction of the depth of the width of the diffusion region. Emitter resistance is reduced by... | 05/13/1997 |
