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| Number | Title | Issue Date |
| 7364971 | Method for manufacturing semiconductor device having super junction construction A semiconductor device includes a body region, a drift region having a first part and a second part, and a trench gate electrode. The body region is disposed on the drift region. The first and second parts extend in an extending direction so that the second part is ... | 04/29/2008 |
| 7358147 | Process for producing SOI wafer There is provided a process for producing an SOI wafer in which, when producing an SOI wafer using Smart Cut technology, the surface can be smoothed after cleaving, the thickness of the SOI layer can be reduced, and the film thickness of the SOI wafer can be made un... | 04/15/2008 |
| 7238577 | Method of manufacturing self-aligned n and p type stripes for a superjunction device A method is provided for obtaining extremely fine pitch N-type and P-type stripes that form the voltage blocking region of a superjunction power device. The stripes are self-aligned and do not suffer from alignment tolerances. The self-aligned, fine pitch of the alt... | 07/03/2007 |
| 6881633 | Method of manufacturing a semiconductor device with an L-shaped/reversed L-shaped gate side-wall insulating film Provided is a semiconductor device, comprising a gate electrode formed on a semiconductor substrate, source/drain diffusion layers formed on both sides of the gate electrode, a gate electrode side-wall on the side of the source/drain diffusion layer and a gate side-... | 04/19/2005 |
| 6677208 | Transistor with bottomwall/sidewall junction capacitance reduction region and method A method of fabricating a transistor comprises forming a gate structure outwardly of a semiconductor substrate, wherein the gate structure comprises a gate, a gate insulator and sidewalls and forming source region and a drain region in the substrate using... | 01/13/2004 |
| 6677643 | Super-junction semiconductor device A super-junction semiconductor is provided that facilitates easy mass-production thereof, reducing the tradeoff relation between the on-resistance and the breakdown voltage, obtaining a high breakdown voltage and reducing the on-resistance to increase the... | 01/13/2004 |
| 6677642 | Field effect transistor structure and method of manufacture A field effect transistor structure is formed with a body semiconductor layer (5) having source (9), body (7), drift region and drain (11). An upper semiconductor layer (21) is separated from the body by an oxide layer (17). The upper semiconductor layer ... | 01/13/2004 |
| 6670681 | Semiconductor structures A method of implanting dopants into a semiconductor structure wherein a lateral periphery of a photoresist mask is shifted after implanting a first dopant and prior to implanting a second dopant. The invention also includes semiconductor structures having... | 12/30/2003 |
| 6670103 | Method for forming lightly doped diffusion regions A method for forming a lightly doped diffusion region comprises providing a substrate structure. A first photoresist layer, having a lightly doped diffusion region pattern, is formed on the substrate structure. Next, dopants of a first type conductivity a... | 12/30/2003 |
| 6664593 | Field effect transistor structure and method of manufacture A field effect transistor structure is formed with a body semiconductor layer (1) having source (3), channel (7), drift region (9) and drain (5). An upper metallisation layer (15, 17) is separated from the body by an oxide layer (11). The upper metallisat... | 12/16/2003 |
| 6642581 | Semiconductor device comprising buried channel region A semiconductor device includes a gate insulating film formed on a semiconductor substrate between first diffusion layers, a gate electrode including a first gate portion formed on the gate insulating film and a second gate portion formed on the first gat... | 11/04/2003 |
| 6624455 | Semiconductor device and method of manufacturing the same including drain pinned along channel width In a semiconductor device, pining regions 105 are disposed along the junction portion of a drain region 102 and a channel forming region 106 locally in a channel width direction. With this structure, because the spread of a depletion layer from a drain si... | 09/23/2003 |
| 6614075 | Semiconductor device and method of manufacturing the same A semiconductor device includes a source region 4, a channel region 8, a drain region 5 and a gate electrode which is patterned so that its side wall is tapered to be more narrow toward the top. A drift region 22 is formed between the channel region 8 ... | 09/02/2003 |
| 6614089 | Field effect transistor In an N-MOSFET having a Double RESURF structure, an n-drift layer and a p-base layer are formed to be adjacent to each other in the surface of a p-semiconductor active layer. An n+ -drain layer and a p-RESURF layer are formed in the surface of ... | 09/02/2003 |
| 6610585 | Method for forming a retrograde implant A method of ion implantation is provided. The method comprising: providing a substrate; forming a masking image having a sidewall on the substrate; forming a blocking layer on the substrate and on the masking image; and performing a retrograde ion implant... | 08/26/2003 |
| 6600197 | Thin film transistor having a heat sink that exhibits a high degree of heat dissipation effect In forming a pair of impurity regions in an active layer, an intrinsic or substantially intrinsic region having a double-sided comb shape is also formed by using a proper mask. The intrinsic or substantially intrinsic region is composed of a portion that ... | 07/29/2003 |
| 6586799 | Semiconductor device and method of manufacturing same A semiconductor device includes a semiconductor layer having a main surface (100a), a first region (101) of a first conductivity type, a second region (102) of a second conductivity type, and a third region (103) of the second conductivity type, the first... | 07/01/2003 |
| 6555894 | Device with patterned wells and method for forming same In a semiconductor substrate having a top surface and a PN junction between a first region of one conductivity type formed by masked diffusion into a semiconductor from the surface and a second region of opposite conductivity type formed into a first port... | 04/29/2003 |
| 6521953 | Semiconductor CMOS structures with an undoped region A method of implanting dopants into a semiconductor structure is described wherein a lateral periphery of a photoresist mask is shifted after implanting a first dopant and prior to implanting a second dopant. Also semiconductor structures having two doped... | 02/18/2003 |
| 6504230 | Compensation component and method for fabricating the compensation component A compensating component and a method for the production thereof are described. Compensating regions are produced by implanting sulfur or selenium in a p-conductive semiconductor layer or, are provided as p-conductive regions, which are doped with indium,... | 01/07/2003 |
| 6500723 | Method for forming a well under isolation and structure thereof A number of small wells under the isolation layer are formed using the same mask made of photoresist and implant step that is used for the regular wells. The small wells are formed close enough together so that they merge during normal subsequent semicond... | 12/31/2002 |
| 6486014 | Semiconductor device and method of manufacturing the same In a semiconductor device, pining regions 105 are disposed along the junction portion of a drain region 102 and a channel forming region 106 locally in a channel width direction. With this structure, because the spread of a depletion layer from a drain si... | 11/26/2002 |
| 6481119 | Apparatus for removing organic antireflection coating An organic antireflection coating is formed on a semiconductor substrate. A resist film is formed on the semiconductor substrate through the organic antireflection coating. The resist film is patterned for forming a resist pattern having an opening. A par... | 11/19/2002 |
| 6479372 | Method for avoiding water marks formed during cleaning after well implantation A method for forming a hydrophilic surface on a silicon substrate during cleaning step after well implantation comprises providing a silicon substrate and an insulating layer is deposited thereon for mask alignment requirement. A photoresist layer is form... | 11/12/2002 |
| 6479339 | Use of a thin nitride spacer in a split gate embedded analog process A mixed voltage CMOS process for high reliability and high performance core transistors and input-output and analog transistors with reduced mask steps. A patterned silicon nitride film 160 is used to selectively mask various implant species during the fo... | 11/12/2002 |
| 6444549 | Thermal processing of semiconductor devices Upon fabrication of semiconductor devices, a semiconductor substrate is subjected to ion implantation with high energy. Subsequent annealing of the ion-implanted semiconductor substrate, when conducted by heating the substrate to a temperature of from 1,0... | 09/03/2002 |
| 6440799 | Semiconductor structures, methods of implanting dopants into semiconductor structures and methods of forming CMOS constructions The invention includes a method of implanting dopants into a semiconductor structure wherein a lateral periphery of a photoresist mask is shifted after implanting a first dopant and prior to implanting a second dopant. The invention also includes semicond... | 08/27/2002 |
| 6436772 | Method of manufacturing semiconductor device having memory cell transistors A plurality of diffusion layers extending in a first direction is formed at a surface of a semiconductor substrate in a cell region to be provided with the memory cell transistors. A plurality of gate electrodes extending in a second direction perpendicul... | 08/20/2002 |
| 6432763 | Field effect transistor having doped gate with prevention of contamination from the gate during implantation For fabricating a field effect transistor on a semiconductor substrate, a gate dielectric of the field effect transistor is formed on a semiconductor substrate. A doped gate electrode, which may be comprised of silicon germanium (SiGe) for example, is for... | 08/13/2002 |
| 6429099 | Implementing contacts for bodies of semiconductor-on-insulator transistors A method and semiconductor structure are provided for implementing body contacts for semiconductor-on-insulator transistors. A bulk semiconductor substrate is provided. A mask is applied to the bulk semiconductor substrate to block an insulating implant l... | 08/06/2002 |
| 6420247 | Method of forming structures on a semiconductor including doping profiles using thickness of photoresist A method of forming structures on a semiconductor wafer (1) by lithographic and subsequent ion implant steps comprises the steps of: deposition of a resist layer (5) on a surface of said semiconductor wafer (1), exposing said resist layer to light of a pr... | 07/16/2002 |
| 6407433 | Preventing gate oxide damage by post poly definition implantation while gate mask is on A method for preventing gate oxide damage caused by post poly definition implantation is disclosed. It is shown that the antenna ratio that is correlatable to oxide damage can be reduced and made to approach zero by implementing a mask layout during ion i... | 06/18/2002 |
| 6403438 | Process for manufacturing a resistive structure used in semiconductor integrated circuits A process for manufacturing a resistive structure that has a polysilicon strip laid above a semiconductor substrate is presented. The process begins by using a mask to cover the polysilicon strip. Then, several apertures are made in the mask until portion... | 06/11/2002 |
| 6391732 | Method to form self-aligned, L-shaped sidewall spacers A new method of forming silicon nitride sidewall spacers has been achieved. In addition, a new device profile for a silicon nitride sidewall spacer has been achieved. An isolation region is provided overlying a semiconductor substrate. Polysilicon traces ... | 05/21/2002 |
| 6383876 | MOS device having non-uniform dopant concentration and method for fabricating the same A metal-oxide-semiconductor (MOS) device in which the nonuniform dopant concentration in the channel region is obtained by means of ion implantation through a polysilicon gate electrode of nonuniform cross section, which is itself obtained by oxidizing th... | 05/07/2002 |
| 6376321 | Method of making a pn-junction in a semiconductor element A pn-junction in a semiconductor element is made in that, within a zone of a first conductivity type, by means of implantation, a first and second zone of a second conductivity type are formed which are initially separated from each other, with subsequent... | 04/23/2002 |
| 6376289 | Method of manufacturing a semiconductor device The invention relates to a method of manufacturing a high-voltage element, in particular, but not exclusively an LDMOS transistor in SOI with a drift region (13) which has a linearly increasing doping concentration between a back-gate region (8) and a dra... | 04/23/2002 |
| 6365472 | Semiconductor device and method of manufacturing the same A semiconductor device comprises an LDD structure MOS transistor wherein the formation of defects due to ion implantation at the edge of the side wall of the gate electrode is suppressed. In order to perform the ion implantation for forming the source and... | 04/02/2002 |
| 6365525 | Method of fabricating a semiconductor insulation layer The invention defines a method for fabricating a semiconductor insulation layer: A semiconductor substrate is first provided; an insulation layer is applied by way of region-by-region or whole-area application to the semiconductor substrate; impurity ions... | 04/02/2002 |
| 6362061 | Method to differentiate source/drain doping by using oxide slivers A method of manufacturing devices with source, drain and extension regions is provided. To achieve in the extensions a depth and dopant levels different from the source and drain regions, a channel-shaped oxide structure is formed surrounding a polysilico... | 03/26/2002 |
