Bizarre Patents
A fork with timer for providing a cue to a user after an elapsed period of time for indicating that another bite of food using the fork may be taken.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7410876 | Methodology to reduce SOI floating-body effect A method for making a semiconductor device, comprising (a) providing a structure comprising a gate electrode (207) disposed on a substrate (203); (b) creating first (213) and second (214) pre-amorphization implant regions in the substrate... | 08/12/2008 |
| 7387942 | Substrate isolation in integrated circuits Substrate isolation trench (224) are formed in a semiconductor substrate (120). Dopant (e.g. boron) is implanted into the trench sidewalls by ion implantation to suppress the current leakage along the sidewalls. During the ion implantation, the transis... | 06/17/2008 |
| 7378323 | Silicide process utilizing pre-amorphization implant and second spacer A gate electrode is formed on a substrate with a gate insulating layer therebetween. A liner is then deposited on sidewalls of the gate electrode. Source/drain extensions are implanted into the substrate. A first spacer is then formed on the liner. Deep source/drain... | 05/27/2008 |
| 7371648 | Method for manufacturing a transistor device having an improved breakdown voltage and a method for manufacturing an integrated circuit using the same The present invention provides a method for manufacturing a transistor device, and a method for manufacturing an integrated circuit including the same. The method for manufacturing the transistor device, among other elements, includes forming a gate structure over a... | 05/13/2008 |
| 7351637 | Semiconductor transistors having reduced channel widths and methods of fabricating same A method of forming a channel in a semiconductor device including forming an opening in a masking layer to expose a portion of an underlying semiconductor layer through the opening is provided. The method further includes disposing a screening layer and implanting a... | 04/01/2008 |
| 7351627 | Method of manufacturing semiconductor device using gate-through ion implantation Disclosed herein is a method of manufacturing a semiconductor device via gate-through ion implantation, comprising forming a gate stack on a semiconductor substrate and performing ion implantation for control of the threshold voltage and junction ion implantation fo... | 04/01/2008 |
| 7326622 | Method of manufacturing semiconductor MOS transistor device A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate having a main surface is prepared. A gate dielectric layer is formed on the main surface. A gate electrode is patterned on the gate dielectric layer... | 02/05/2008 |
| 7297581 | SRAM formation using shadow implantation A method of doping fins of a semiconductor device that includes a substrate includes forming multiple fin structures on the substrate, each of the fin structures including a cap formed on a fin. The method further includes performing a first tilt angle implant proce... | 11/20/2007 |
| 7291535 | Method and apparatus for fabricating semiconductor device A method for fabricating a semiconductor device includes the steps of: forming a semiconductor region of a first conductive type on a semiconductor wafer; forming a gate electrode on the semiconductor region; on the semiconductor region, forming a first insulating f... | 11/06/2007 |
| 7282415 | Method for making a semiconductor device with strain enhancement A semiconductor device with strain enhancement is formed by providing a semiconductor substrate and an overlying control electrode having a sidewall. An insulating layer is formed adjacent the sidewall of the control electrode. The semiconductor substrate and the co... | 10/16/2007 |
| 7265418 | Semiconductor devices having field effect transistors A semiconductor device having a field effect transistor and a method of fabricating the same. In-situ doped epitaxial patterns are respectively formed at both sidewalls of a protruded channel pattern from a substrate by performing an in-situ doped epitaxial growth p... | 09/04/2007 |
| 7253054 | One time programmable EPROM for advanced CMOS technology A one time programmable (OTP) electrically programmable read only memory (EPROM) transistor (100) having an increased breakdown voltage (BVdss) is disclosed. The increased breakdown voltage reduces the probability that the OTP EPROM (100) will breakdow... | 08/07/2007 |
| 7208383 | Method of manufacturing a semiconductor component An insulated gate field effect transistor having reduced gate-drain overlap and a method for manufacturing the insulated gate field effect transistor. A gate structure is formed on a major surface of a semiconductor substrate. A source extension region and a drain e... | 04/24/2007 |
| 6703659 | Low voltage programmable and erasable flash EEPROM A new method of fabricating and programming and erasing a Flash EEPROM memory cell is achieved. A semiconductor substrate is provided. A tunneling oxide layer is formed overlying said semiconductor substrate. A first polysilicon layer is deposited overlyi... | 03/09/2004 |
| 6699744 | Method of forming a MOS transistor of a semiconductor device The disclosure relates to a method of forming a MOS transistor of a semiconductor device and, more particularly, to a method of forming a PMOS transistor of a semiconductor device that minimizes temporary reinforcement and diffusion of dopants for control... | 03/02/2004 |
| 6696734 | LDD high voltage MOS transistor A semiconductor device has a gate electrode formed on P type semiconductor substrate through a gate insulation film, a low concentration N- type drain region formed so as to be adjacent to the gate electrode, a high concentration N+ type drain region sepa... | 02/24/2004 |
| 6693012 | Method and device to reduce gate-induced drain leakage (GIDL) current in thin gate oxide MOSFETs A process for the fabrication of an integrated circuit which provides a FET device having reduced GIDL current is described. A semiconductor substrate is provided wherein active regions are separated by an isolation region, and a gate oxide layer is form ... | 02/17/2004 |
| 6693338 | Power semiconductor device having RESURF layer A semiconductor device includes a drain layer, first and second drift layers, a RESURF layer, a drain electrode, a base layer, a source layer, a source electrode, and a gate electrode. The first drift layer is formed on the drain layer. The second drift l... | 02/17/2004 |
| 6682980 | Fabrication of abrupt ultra-shallow junctions using angled PAI and fluorine implant The present invention is directed to a method of forming a PMOS transistor within a semiconductor substrate, and comprises forming a gate over an n-type portion of the semiconductor substrate, thereby defining a source region and a drain region in the sem... | 01/27/2004 |
| 6677212 | Elevated source/drain field effect transistor and method for making the same A gate oxide film (23), a gate electrode (24) and a gate cap insulating film (25) are stacked on an active region of a p-type semiconductor substrate (21), and an insulating side wall (29) is formed, followed by BF2 ion implantation. Thus, a su... | 01/13/2004 |
| 6674137 | Semiconductor device and its manufacturing method A semiconductor device is disclosed that can include a gate electrode (6) having a lower layer (6a) and a higher layer (6b), a mask insulating film (7) formed over a higher layer (6b). A side surface insulating film (9) may be formed on sides of a gate el... | 01/06/2004 |
| 6667554 | Expanded implantation of contact holes A method of forming electrical contacts includes the step of implanting ions into a contact hole at an angle to create an enlarged plug enhancement region at the bottom of a contact hole. Thus, even if the contact hole is misaligned, over-sized, or over-e... | 12/23/2003 |
| 6667513 | Semiconductor device with compensated threshold voltage and method for making same A semiconductor device may include a channel region formed between a source and a drain region. One or more first pockets may be formed in the channel region adjacent to junctions. The first pockets may be doped with a dopant of the first conductivity typ... | 12/23/2003 |
| 6667512 | Asymmetric retrograde halo metal-oxide-semiconductor field-effect transistor (MOSFET) An asymmetric retrograde HALO Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) includes a semiconductor substrate. A gate is formed over the substrate, the gate defining a channel thereunder in the substrate having a source side and a drain side... | 12/23/2003 |
| 6664588 | NROM cell with self-aligned programming and erasure areas A memory cell has two diffusion areas in a substrate with a channel therebetween. The memory cell also includes a trapping dielectric layer at least over the channel, a gate at least above the trapping dielectric layer, and an implant in the substrate ada... | 12/16/2003 |
| 6660605 | Method to fabricate optimal HDD with dual diffusion process to optimize transistor drive current junction capacitance, tunneling current and channel dopant loss Methods are discussed for forming a transistor comprising a source/drain region having both a graded HDD portion and a sharp HDD portion in a semiconductor substrate. The method comprises a dual diffusion process, wherein a gate structure is provided over... | 12/09/2003 |
| 6660595 | Implantation method for simultaneously implanting in one region and blocking the implant in another region A method of fabricating different transistor structures with the same mask. A masking layer (214) has two openings (204, 202) that expose two transistor areas (304,302). The width of the second opening (202) is adjusted such that the angled implant is sub... | 12/09/2003 |
| 6653656 | Semiconductor device formed on insulating layer and method of manufacturing the same In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an uppe... | 11/25/2003 |
| 6649459 | Method for manufacturing a semiconductor component The invention relates to a method for producing a semiconductor component including semiconductor areas of different conductivity types which are alternately positioned in a semiconductor body. The semiconductor areas of different conductivity types exten... | 11/18/2003 |
| 6649966 | Quantum dot of single electron memory device and method for fabricating thereof A method for fabricating a quantum dot, which can be used to fabricate a single electron memory device. The method includes forming a first insulation layer on a semiconductor layer, then forming a second insulation layer on the first insulation layer. Ne... | 11/18/2003 |
| 6649460 | Fabricating a substantially self-aligned MOSFET The present invention includes methods and structures for forming at least a substantially self-aligned MOSFET. According to the present invention, a method of fabricating a semiconductor device includes providing a substrate; providing first materials (s... | 11/18/2003 |
| 6645806 | Methods of forming DRAMS, methods of forming access transistors for DRAM devices, and methods of forming transistor source/drain regions The invention includes a DRAM device. The device has an access transistor construction, and the access transistor construction has a pair of source/drain regions. A halo region is associated with one of the source/drain regions of the access transistor co... | 11/11/2003 |
| 6642122 | Dual laser anneal for graded halo profile Short-channel effects are controlled by forming abrupt, graded halo profiles. Embodiments include sequentially forming deep source/drain regions, ion implanting to form first deep amorphized regions, ion implanting an impurity into the first deep amorphiz... | 11/04/2003 |
| 6642118 | Method for eliminating polysilicon residue by fully converting the polysilicon into silicon dioxide A method for eliminating polysilicon residue is provided by converting the polysilicon residue into silicon dioxide in two steps. A tilted ion implantation step is performed to implant oxygen ions into the polysilicon residue to rich oxygen containing of ... | 11/04/2003 |
| 6639288 | Semiconductor device with a particular conductor arrangement A tungsten nitride (6b) is provided also on side surface of a tungsten (6c), to increase an area where the tungsten (6c) and the tungsten nitride (6b) are in contact with each other. On a gate insulating film (2), a polysilicon side wall (5) having high a... | 10/28/2003 |
| 6638825 | Method for fabricating a high voltage device A high voltage device and a method for fabricating the same are disclosed, which improves voltage-resistant characteristics to protect against high voltage applied to a gate electrode. The high voltage device includes a semiconductor substrate having firs... | 10/28/2003 |
| 6632727 | Expanded implantation of contact holes A method of forming electrical contacts includes the step of implanting ions into a contact hole at an angle to create an enlarged plug enhancement region at the bottom of a contact hole. Thus, even if the contact hole is misaligned, over-sized, or over-e... | 10/14/2003 |
| 6630385 | MOSFET with differential halo implant and annealing strategy A method for improving the channel doping profile of deep-submicron field effect transistors and MOSFETs. The method involves dual halo implants annealed at different temperatures to improve the threshold voltage roll-off characteristics of MOSFETs of app... | 10/07/2003 |
| 6627499 | Semiconductor device and method of manufacturing the same Formed in a part of the base region is an impurity diffusion region extending in a vertical direction and having an impurity concentration lower than that in the other portion of the base region. By the formation of the impurity diffusion region, the depl... | 09/30/2003 |
| 6624469 | Vertical MOS transistor having body region formed by inclined ion implantation There is provided a vertical MOS transistor in which a high frequency characteristic is improved, a low voltage operation is realized, and a stable characteristic with less fluctuation is obtained. After trench gate oxidation, a body is formed at a side w... | 09/23/2003 |
