Class 257/E21.337 - Through-implantation (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.336. This
No. of patents: 317
Last issue date: 07/22/2008

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Number	Title	Issue Date
7402495	Method for manufacturing a semiconductor device A method of manufacturing a semiconductor device includes forming a first semiconductor region of a first conductive type and a second semiconductor region of a second conductive type in a predetermined region of the semiconductor substrate of a first conductive typ...	07/22/2008
7384834	Semiconductor device and a method of manufacturing the same A semiconductor device and a method of manufacturing such a semiconductor device having a field effect transistor with improved current driving performance (e.g., an increase of drain current) of the field effect transistor comprising the steps of ion implanting an ...	06/10/2008
7319061	Method for fabricating electronic device In a method for fabricating an electronic device including a transistor with a drain extension structure, a correspondence between a size of a gate electrode of the transistor and ion implantation conditions or heat treatment conditions for forming the drain extensi...	01/15/2008
7282416	Method for fabricating electronic device In a method for fabricating an electronic device including a transistor with a drain extension structure, a correspondence between a size of a gate electrode of the transistor and ion implantation conditions or heat treatment conditions for forming the drain extensi...	10/16/2007
7247547	Method of fabricating a field effect transistor having improved junctions A method of forming a field effect transistor is provided which includes forming an amorphized semiconductor region having a first depth from a single-crystal semiconductor region and subsequently forming a first gate conductor above a channel portion of the amorphi...	07/24/2007
7223663	MOS transistors and methods of manufacturing the same MOS transistors having a low junction capacitance between their halo regions and their source/drain extension regions and methods for manufacturing the same are disclosed. A disclosed MOS transistor includes: a semiconductor substrate of a first conductivity type; a...	05/29/2007
7217136	Printed circuit board with right-angled trace and method for making the same A printed circuit board having right-angled trace and a method for making the right-angled trace is to apply semi-conductor material and form an interface with a P-type semi-conductive layer and a N-type semi-conductive layer. The semi-conductive right-angled interf...	05/15/2007
7199030	Method of manufacturing semiconductor device An impurity is ion-implanted with a silicon nitride film formed on a silicon substrate as a mask film to form a source/drain layer of a MOS transistor. Heat treatment for activating the impurity is done as it is without removing the silicon nitride film to thereby p...	04/03/2007
7192789	Method for monitoring an ion implanter A method for monitoring an ion implanter is disclosed. In one embodiment, the method comprises providing a wafer, forming a barrier layer on the surface of the wafer wherein the barrier layer has a substantial blocking effect on ion implantation, performing an ion i...	03/20/2007
7157357	Methods of forming halo regions in NMOS transistors Disclosed are methods of forming a halo region in n-channel type MOS (NMOS) transistors. In one example, the method includes forming, on a channel region of a semiconductor substrate, a structure having a gate insulation film pattern and a gate conductive film patte...	01/02/2007
7135392	Thermal flux laser annealing for ion implantation of semiconductor P-N junctions A method for forming P-N junctions in a semiconductor wafer includes ion implanting dopant impurities into the wafer and annealing the wafer using a thermal flux laser annealing apparatus that includes an array of semiconductor laser emitters arranged in plural para...	11/14/2006
6696332	Bilayer deposition to avoid unwanted interfacial reactions during high K gate dielectric processing Methods are disclosed for forming gate dielectrics for MOSFET transistors, wherein a bilayer deposition of a nitride layer and an oxide layer are used to form a gate dielectric stack. The nitride layer is formed on the substrate to prevent oxidation of th...	02/24/2004
6693014	Method of improving static refresh A double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface. Next, a first pair of diffus...	02/17/2004
6690060	Field effect transistor and method of fabricating the same by controlling distribution condition of impurity region with implantation of additional ion A first object of the present invention is to provide an insulated gate field effect transistor which realizes reductions in the junction depth and the resistance of source and drain junction regions beneath a gate electrode. Another object is to provide ...	02/10/2004
6682980	Fabrication of abrupt ultra-shallow junctions using angled PAI and fluorine implant The present invention is directed to a method of forming a PMOS transistor within a semiconductor substrate, and comprises forming a gate over an n-type portion of the semiconductor substrate, thereby defining a source region and a drain region in the sem...	01/27/2004
6680243	Shallow junction formation A method for forming shallow junctions in a substrate. The substrate is masked with a first mask to selectively cover first portions of the substrate and selectively expose second portions of the substrate. A first dopant is implanted substantially within...	01/20/2004
6677194	Method of manufacturing a semiconductor integrated circuit device A low threshold voltage NMIS area and a high threshold voltage PMIS area are set by a photoresist mask also used for well formation. Using a photoresist mask with openings for the NMIS and PMIS, the NMIS and PMIS areas are set by one ion implantation step...	01/13/2004
6670254	Method of manufacturing semiconductor device with formation of a heavily doped region by implantation through an insulation layer A method of manufacturing semiconductor devices. A gate structure is formed over a substrate. A dopant implantation is carried out to form a lightly doped region in the substrate on each side of the gate structure. An insulation layer is formed over the s...	12/30/2003
6670252	Method of manufacturing semiconductor device A method of manufacturing a semiconductor device which reduces the number of impurity implantations. A buffer film for reducing a quantity of an impurity implantation is provided adjacent to an MIS gate structure over a surface of a semiconductor substrat...	12/30/2003
6660608	Method for manufacturing CMOS device having low gate resistivity using aluminum implant A CMOS device (10) having p-channel and n-channel transistors with aluminum implanted gates (20). When making the device (10), aluminum is non-selectively implanted to form a source and drain for the n-channel transistor and to reduce the resistivity of t...	12/09/2003
6656800	Method of manufacturing semiconductor device including process for implanting impurities into substrate via MOS transistor gate electrode and gate insulation film A gate oxide film and a first layer of a multi-layered gate electrode are stacked on a substrate and by a gate prefabrication technique, an oxide layer of an element isolation region is formed in a self-alignment manner using the first layer of the gate e...	12/02/2003
6657267	Semiconductor device and fabrication technique using a high-K liner for spacer etch stop A semiconductor device and method of fabrication are disclosed. The semiconductor device includes a liner composed of a high-K material. The liner has a portion separating a sidewall spacer from a gate and a portion separating the sidewall spacer from a l...	12/02/2003
6649308	Ultra-short channel NMOSFETS with self-aligned silicide contact The ultra-short channel transistor in a semiconductor substrate includes a gate structure that is formed on the substrate. Side-wall spacers are formed on the side walls of the gate structure as an impurities-diffusive source. Source and drain regions are...	11/18/2003
6638803	Semiconductor device and method for manufacturing the same Isolation regions 12 are formed on a silicon substrate 10 to isolate NMOS and PMOS regions in which to form NMOS and PMOS transistors respectively. A silicon oxide film 14 and an amorphous silicon film 16 are formed as a gate insulating film on the silico...	10/28/2003
6638822	Method for forming the self-aligned buried N+ type to diffusion process in ETOX flash cell A method for forming the self-aligned buried N+ -type to diffusion process in ETOX flash cell is disclosed. The method at least includes the following steps. First of all, a substrate is provided having a pad oxide layer thereon, a dielectric l...	10/28/2003
6624489	Formation of silicided shallow junctions using implant through metal technology and laser annealing process A method for producing MOS type transistors with deep source/drain junctions and thin, silicided contacts with desireable interfacial and electrical properties. The devices are produced by a method that involves pre-amorphization of the gate, source and d...	09/23/2003
6610585	Method for forming a retrograde implant A method of ion implantation is provided. The method comprising: providing a substrate; forming a masking image having a sidewall on the substrate; forming a blocking layer on the substrate and on the masking image; and performing a retrograde ion implant...	08/26/2003
6611031	Semiconductor device and method for its manufacture A semiconductor device is disclosed including an insulated gate field effect transistor (IGFET) having a gate insulating layer (2), a gate electrode (3), and a source-drain layer (5). The IGFET may include a bird's beak insulating film (4) in a region in ...	08/26/2003
6607958	Semiconductor device and method of manufacturing the same Disclosed is a semiconductor device, comprising a semiconductor substrate, an insulating film and a gate electrode formed on the semiconductor substrate, source-drain regions formed in the semiconductor substrate, and a metal oxide layer formed selectivel...	08/19/2003
6589336	Production method for silicon epitaxial wafer and silicon epitaxial wafer Performing the post-implantation annealing for recovering crystallinity in a hydrogen atmosphere can successfully suppress the surface roughening on the ion-implanted layers without pre-implantation oxidation. This allows omission of the pre-implantation ...	07/08/2003
6579770	Sidewall process and method of implantation for improved CMOS with benefit of low CGD, improved doping profiles, and insensitivity to chemical processing A transistor (30) and method for forming a transistor using an edge blocking material (24) is disclosed herein. The edge blocking material (24) may be located adjacent a gate (22) or disposable gate or may be part of a disposable gate. During an angled po...	06/17/2003
6518625	Semiconductor device An n-type impurity layer is formed on a boundary portion between a source/drain and a field oxide film in a portion deeper than the source/drain. Even if a metal silicide layer such as a Co silicide layer extends into a portion under the field oxide film ...	02/11/2003
6518136	Sacrificial polysilicon sidewall process and rapid thermal spike annealing for advance CMOS fabrication A process for making abrupt, e.g.	02/11/2003
6506650	Method of fabrication based on solid-phase epitaxy for a MOSFET transistor with a controlled dopant profile A MOSFET transistor and method of fabrication are described for engineering the channel dopant profile within a MOSFET transistor utilizing a single deep implantation step and solid-phase epitaxy. The method utilizes the formation of an L-shaped spacer ha...	01/14/2003
6503805	Channel implant through gate polysilicon A field effect transistor having a doped region in the substrate immediately underneath the gate of the transistor and interposed between the source and drain of the transistor is provided. The doped region has a retrograde dopant profile such that the do...	01/07/2003
6504232	Integrated circuit components thereof and manufacturing method The present invention relates to a collector pin and a trench in an integrated circuit intended for high speed communication, and to a manufacturing method for these items. The collector pin is achieved by creating an area which is implantation damaged or...	01/07/2003
6489209	Manufacturing method of LDD-type MOSFET After a first insulating film is formed only on the top surface or at least on the entire surface of a polysilicon gate electrode, first impurity ions are implanted into a semiconductor substrate from above the entire substrate to provide lightly doped so...	12/03/2002
6475815	Method of measuring temperature, method of taking samples for temperature measurement and method for fabricating semiconductor device An amorphous region is formed by implanting an impurity such as As into a semiconductor substrate having a natural oxide film. The amorphous region is divided into a heavily doped oxygen region in which the concentration of oxygen is equal to or higher th...	11/05/2002
6476454	Semiconductor device and method of manufacturing the same Disclosed is a semiconductor device, comprising a semiconductor substrate, an insulating film and a gate electrode formed on the semiconductor substrate, source-drain regions formed in the semiconductor substrate, and a metal oxide layer formed selectivel...	11/05/2002
6472281	Method for fabricating semiconductor device using a CVD insulator film A gate insulator film and a gate electrode are formed on an Si substrate, and a CVD insulator film is deposited thereon to cover the gate electrode. Then, arsenic ions are implanted into the Si substrate from above the CVD insulator film to form LDD layer...	10/29/2002

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Class 257/E21.337 - Through-implantation (EPO)