Class 257/E21.335 - In Group IV semiconductor (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.334. This
No. of patents: 390
Last issue date: 10/07/2008

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Number	Title	Issue Date
7432541	Metal oxide semiconductor field effect transistor A metal oxide semiconductor field effect transistor (MOSFET) is disclosed. The MOSFET includes a semiconductor substrate, a germanium layer formed by implanting germanium (Ge) ions into the semiconductor substrate, an epitaxial layer doped with high concentration im...	10/07/2008
7432146	Semiconductor device and manufacturing method thereof To make it possible to obtain a sharp impurity profile without presenting a disadvantage such as an increase in parasitic resistance or the like using a laser annealing method to thereby meet sufficiently the requirements for making a semiconductor element finer and...	10/07/2008
7429771	Semiconductor device having halo implanting regions A MIS-type semiconductor device includes a p-type semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and n-type diffused source and drain layers formed in regions of the semicon...	09/30/2008
7402484	Methods for forming a field effect transistor Methods for forming a field effect transistor are disclosed. An illustrated method comprises: forming a gate electrode on a substrate; and forming a nitride layer on at least a part of the gate electrode and the substrate. ...	07/22/2008
7384834	Semiconductor device and a method of manufacturing the same A semiconductor device and a method of manufacturing such a semiconductor device having a field effect transistor with improved current driving performance (e.g., an increase of drain current) of the field effect transistor comprising the steps of ion implanting an ...	06/10/2008
7371648	Method for manufacturing a transistor device having an improved breakdown voltage and a method for manufacturing an integrated circuit using the same The present invention provides a method for manufacturing a transistor device, and a method for manufacturing an integrated circuit including the same. The method for manufacturing the transistor device, among other elements, includes forming a gate structure over a...	05/13/2008
7358167	Implantation process in semiconductor fabrication A semiconductor device is formed by performing an amorphizing ion implantation to implant dopants of a first conductivity type into a semiconductor body. The first ion implantation causes a defect area (e.g., end-of-range defects) within the semiconductor body at a ...	04/15/2008
7358196	Wet chemical treatment to form a thin oxide for high k gate dielectrics Described herein are methods of forming a thin silicon dioxide layer having a thickness of less than eight angstroms on a semiconductor substrate to form the bottom layer of a gate dielectric. A silicon dioxide layer having a thickness of less than eight angstroms m...	04/15/2008
7339214	Methods and apparatus for inducing stress in a semiconductor device Methods and apparatus are disclosed for selectively inducing stress in a semiconductor device, wherein a first region of a substrate is implanted so as to induce stress in a second region. An electrical device is formed at least partially in the second region, where...	03/04/2008
7247547	Method of fabricating a field effect transistor having improved junctions A method of forming a field effect transistor is provided which includes forming an amorphized semiconductor region having a first depth from a single-crystal semiconductor region and subsequently forming a first gate conductor above a channel portion of the amorphi...	07/24/2007
7118981	Method of fabricating an integrated silicon-germanium heterobipolar transistor and an integrated silicon-germanium heterobipolar transistor In a method of fabricating an integrated silicon-germanium heterobipolar transistor a silicon dioxide layer arranged between a silicon-germanium base layer and a silicon emitter layer is formed by means of Rapid Thermal Processing (RTP) to ensure enhanced component ...	10/10/2006
7091114	Semiconductor device and method of manufacturing the same Disclosed is a method for manufacturing a semiconductor device comprising implanting ions of an impurity element into a semiconductor region, implanting, into the semiconductor region, ions of a predetermined element which is a group IV element or an element having ...	08/15/2006
6703322	Method of forming multiple oxide layers with different thicknesses in a linear nitrogen doping process Multiple oxide layers with different thicknesses are formed on a semiconductor substrate with a silicon surface, having a first and second region. A sacrificial oxide layer is formed on the silicon surface to cover both the first region and the second reg...	03/09/2004
6703281	Differential laser thermal process with disposable spacers MOSFETs are fabricated with accurately defined, high and uniformly concentrated source/drain regions and extensions employing plural, sequential pre-amorphizing, implanting and laser thermal annealing steps with intervening spacer removal. Embodiments inc...	03/09/2004
6703671	Insulated gate semiconductor device and method of manufacturing the same Impurity regions 110 that can form an energy barrier are artificially and locally disposed in a channel formation region 111. The impurity regions 110 restrain a depletion layer that extends from a drift region 102 toward a channel formation region 111, a...	03/09/2004
6699744	Method of forming a MOS transistor of a semiconductor device The disclosure relates to a method of forming a MOS transistor of a semiconductor device and, more particularly, to a method of forming a PMOS transistor of a semiconductor device that minimizes temporary reinforcement and diffusion of dopants for control...	03/02/2004
6699771	Process for optimizing junctions formed by solid phase epitaxy A method of forming a semiconductor device includes forming at least one amorphous region within an at least partially formed semiconductor device. The method also includes implanting a halogen species in the amorphous region of the at least partially for...	03/02/2004
6696729	Semiconductor device having diffusion regions with different junction depths An aspect of the present invention includes: a gate insulating layer formed on an n-type silicon semiconductor region; a gate electrode formed on the gate insulating layer; a channel region formed immediately below the gate electrode in the semiconductor ...	02/24/2004
6696354	Method of forming salicide A method of forming a salicide. A metal layer is formed on a silicon-based substrate comprising a gate with a spacer on the side wall of the gate and a source/drain is provided. Next, a first thermal treatment is performed to make the portions of the meta...	02/24/2004
6693012	Method and device to reduce gate-induced drain leakage (GIDL) current in thin gate oxide MOSFETs A process for the fabrication of an integrated circuit which provides a FET device having reduced GIDL current is described. A semiconductor substrate is provided wherein active regions are separated by an isolation region, and a gate oxide layer is form ...	02/17/2004
6682992	Method of controlling grain size in a polysilicon layer and in semiconductor devices having polysilicon structures A method of modulating grain size in a polysilicon layer and devices fabricated with the method. The method comprises forming the layer of polysilicon on a substrate; and performing an ion implantation of a polysilicon grain size modulating species into t...	01/27/2004
6682980	Fabrication of abrupt ultra-shallow junctions using angled PAI and fluorine implant The present invention is directed to a method of forming a PMOS transistor within a semiconductor substrate, and comprises forming a gate over an n-type portion of the semiconductor substrate, thereby defining a source region and a drain region in the sem...	01/27/2004
6680250	Formation of deep amorphous region to separate junction from end-of-range defects A method of manufacturing a MOSFET semiconductor device includes forming a gate electrode over a substrate and a gate oxide between the gate electrode and the substrate. Inert dopants are then implanted within the substrate to form amorphized source/drain...	01/20/2004
6670259	Inert atom implantation method for SOI gettering The present invention relates to a method of manufacturing a silicon-on-insulator substrate, comprising the steps of (1) providing a silicon-on-insulator semiconductor wafer having at least one surface of a silicon film; (2) implanting an inert atom into ...	12/30/2003
6670250	MOS transistor and method for forming the same A MOS transistor including a gate poly oxide layer formed to have different thicknesses over the entire surface of a semiconductor substrate and a method for forming the MOS transistor are provided. A gate oxide layer pattern and a gate conductive layer p...	12/30/2003
6653679	Reduced 1/f noise in MOSFETs An improved gate structure for a MOSFET device exhibits a reduced level of 1/f noise or "flicker noise", while maintaining the control of boron penetration into the substrate of the MOSFET device. The gate structure for the MOSFET device includes a gate e...	11/25/2003
6649976	Semiconductor device having metal silicide film and manufacturing method thereof A semiconductor device in which parasitic resistance of source/drain regions can be reduced than the parasitic resistance of the drain region, and manufacturing method thereof, can be obtained. In the semiconductor device, inactivating ions are implanted ...	11/18/2003
6645838	Selective absorption process for forming an activated doped region in a semiconductor A process for activating a doped region (80) or amorphized doped region (34) in a semiconductor substrate (10). The process includes the steps of doping a region of the semiconductor substrate, wherein the region is crystalline or previously amorphized. T...	11/11/2003
6642106	Method for increasing core gain in flash memory device using strained silicon A method of memory device fabrication. In one embodiment, the method of memory device (400) fabrication comprises implanting an element (200) in a substrate (440). The element (200) causes an inherent elongational realignment of atoms in silicon (101,102)...	11/04/2003
6642118	Method for eliminating polysilicon residue by fully converting the polysilicon into silicon dioxide A method for eliminating polysilicon residue is provided by converting the polysilicon residue into silicon dioxide in two steps. A tilted ion implantation step is performed to implant oxygen ions into the polysilicon residue to rich oxygen containing of ...	11/04/2003
6642122	Dual laser anneal for graded halo profile Short-channel effects are controlled by forming abrupt, graded halo profiles. Embodiments include sequentially forming deep source/drain regions, ion implanting to form first deep amorphized regions, ion implanting an impurity into the first deep amorphiz...	11/04/2003
6638802	Forming strained source drain junction field effect transistors By providing a high dose germanium implant and then forming a P-type source/drain extension, a strained source/drain junction may be formed. The strained source/drain junction may be shallower and have lower resistivity in some embodiments....	10/28/2003
6638832	Elimination of narrow device width effects in complementary metal oxide semiconductor (CMOS) devices Neutral conductivity ions, preferably germanium, are implanted through the oxide of a metal oxide semiconductor after isolation formation to provide a nearly constant threshold voltage for transistor operation independent of transistor channel width as de...	10/28/2003
6639288	Semiconductor device with a particular conductor arrangement A tungsten nitride (6b) is provided also on side surface of a tungsten (6c), to increase an area where the tungsten (6c) and the tungsten nitride (6b) are in contact with each other. On a gate insulating film (2), a polysilicon side wall (5) having high a...	10/28/2003
6635517	Use of disposable spacer to introduce gettering in SOI layer A method of forming a self-aligned gettering region within an SOI substrate is provided. Specifically, the inventive method includes the steps of forming a disposable spacer on each vertical sidewall of a patterned gate stack region, the patterned gate st...	10/21/2003
6635950	Semiconductor device having buried boron and carbon regions, and method of manufacture thereof To improve the gettering performance by ion implanting boron and improves the production yield of the semiconductor device by using an epitaxial wafer of good quality suppressing the occurrence of dislocations. For this purpose, an epitaxial wafer in which an ...	10/21/2003
6632728	Increasing the electrical activation of ion-implanted dopants We have found that under certain prescribed conditions a co-implantation process can be effective in increasing the electrical activation of implanted dopant ions. In accordance with one aspect of our invention, a method of making a semiconductor device i...	10/14/2003
6630405	Method of gate patterning for sub-0.1 μm technology A method of gate patterning, including the following steps. A semiconductor structure having an upper silicon layer is provided. The semiconductor structure has a gate conductor region. A first gate oxide layer is formed over the semiconductor structure. ...	10/07/2003
6630385	MOSFET with differential halo implant and annealing strategy A method for improving the channel doping profile of deep-submicron field effect transistors and MOSFETs. The method involves dual halo implants annealed at different temperatures to improve the threshold voltage roll-off characteristics of MOSFETs of app...	10/07/2003
6624017	Manufacturing process of a germanium implanted HBT bipolar transistor A process fabricates a vertical structure high carrier mobility transistor on a substrate of crystalline silicon doped with impurities of the N type, the transistor having a collector region located at a lower portion of the substrate. The process include...	09/23/2003

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Class 257/E21.335 - In Group IV semiconductor (EPO)