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| Number | Title | Issue Date |
| 7354787 | Electrode design and positioning for controlled movement of a moveable electrode and associated support structure A MEMS system including a fixed electrode and a suspended moveable electrode that is controllable over a wide range of motion. In traditional systems where an fixed electrode is positioned under the moveable electrode, the range of motion is limited because the supp... | 04/08/2008 |
| 7224026 | Nanoelectronic devices and circuits Diode devices with superior and pre-settable characteristics and of nanometric dimensions, comprise etched insulative lines (8, 16, 18) in a conductive substrate to define between the lines charge carrier flow paths, formed as elongate channels (20) at... | 05/29/2007 |
| 7091077 | Method of directionally trimming polysilicon width Polysilicon or other material is directionally trimmed using two layers of photoresist and a photoresist etching process, such as ashing. A first layer of photoresist is patterned on a wafer. Portions of the first patterned photoresist are covered with a second laye... | 08/15/2006 |
| 6610582 | Field-assisted fusion bonding A method of field-assisted fusion bonding produces multiple-layer devices. Contacts (301, 303, 305, 307, 309) are placed at various points along different surfaces of a combination of two or more wafers (201, 203, 205, 501, 503, 505, 801, 803). An electri... | 08/26/2003 |
| 6552411 | DC or AC electric field assisted anneal A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate a... | 04/22/2003 |
| 6534748 | Semiconductor purification apparatus and method A method for protecting at least one wafer from contamination, the method including the steps of heating the wafer in an apparatus for semiconductor processing having a reaction core (102), providing a first voltage level to a wafer transfer device (108),... | 03/18/2003 |
| 6514802 | Method of providing a frontside contact to a substrate of SOI device A method for making frontside contact to a substrate through an SOI structure thereon is provided. An etching step is undertaken to form a trench in the SOI structure so as to expose and define a rug surface of the substrate. Then, a thin insulating layer... | 02/04/2003 |
| 6355511 | Method of providing a frontside contact to substrate of SOI device A method for making frontside contact to a substrate through an SOI structure thereon is provided. An etching step is undertaken to form a trench in the SOI structure so as to expose and define a rough surface of the substrate. Then, a thin insulating lay... | 03/12/2002 |
| 6352939 | Method for improving the electrical properties of a gate oxide A method for improving the electrical properties of a gate oxide is disclosed. The method includes the steps of providing a silicon wafer with a gate oxide formed thereon, providing a platinum plate, immersing the silicon wafer and the platinum plate in a... | 03/05/2002 |
| 6306692 | Coplanar type polysilicon thin film transistor and method of manufacturing the same The present invention discloses a method of manufacturing a thin film transistor, including: depositing an amorphous silicon layer, an insulating layer, and a gate metal layer on a substrate sequentially; patterning the insulating layer and the gate metal... | 10/23/2001 |
| 6274465 | DC electric field assisted anneal A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate a... | 08/14/2001 |
| 6136669 | Mobile charge immune process A semi conductor manufacturing process including uniform negative polarity wafer charging to remove or immobilize alkali ions such that the device becomes immune to their presence. The wafer is charged with a corona discharge at a 1MV/cm-2MV/cm bias field... | 10/24/2000 |
| 6127289 | Method for treating semiconductor wafers with corona charge and devices using corona charging A method of treating the surface of a semiconductor wafer is disclosed for making the wafer resistant to particle adhesion, the method involving the application of a uniform corona charge to the wafer surface. The corona charge is deposited on the wafer u... | 10/03/2000 |
| 6017805 | Method of reducing mobile ion contaminants in semiconductor films The present invention provides the broad concept of increasing product performance and reliability by causing the ion contaminants to migrate to a region of the semiconductor film and removing that region (containing a concentration of the ion contaminant... | 01/25/2000 |
| 5972437 | Method for fabricating a thin film semiconductor device To promote the characteristic of an interface between a gate insulating film and a semiconductor and control the threshold voltage, in forming the insulating film, a surface on which the insulating film is to be formed is previously exposed to activated o... | 10/26/1999 |
| 5882953 | Dopant activation of heavily-doped semiconductor by high current densities Dopant activation in heavily boron doped p+ --Si is achieved by applying electric current of high density. The p+ --Si was implanted by a 40 KeV BF2+ at an ion intensity 5.multidot.1015 ions per cm2 ... | 03/16/1999 |
| 5874320 | Method for forming P-type gallium nitride A method for forming P-type gallium nitride is disclosed in the invention. In this method, Mg--H can be completly discomposed by use of an annealing process, thereby entirely dissociating the hydrogen atoms from the gallium nitride, while the nitrogen ato... | 02/23/1999 |
| 5635410 | Bias temperature treatment method The time and labor required for bias temperature (BT) treatment of a semi-conductor wafer is reduced by utilizing apparatus in which turning a switch 40 on connects a first d.c. power source 30 to apply a positive high voltage between a first wire 20 and ... | 06/03/1997 |
| 5516731 | High-temperature bias anneal of integrated circuits for improved radiation hardness and hot electron resistance A technique for improving the radiation hardness and hot-electron resistance of a CMOS integrated circuit is described whereby undesirable hydrogen ions may be vented through any holes, such as contact holes, in an overlying passivation layer by applying ... | 05/14/1996 |
| 4874711 | Method for altering characteristics of active semiconductor devices Method for altering an electrical characteristic of a circuit having at least one active semiconductor device involves applying at least one pulse--a voltage pulse, a current pulse, an energy pulse, or a power pulse and so forth--across the active semicon... | 10/17/1989 |
| 4870472 | Method for resistor trimming by metal migration A method for trimming a diffused or implanted resistor located within an integrated circuit is disclosed. This technique for trimming a resistor requires the use of high current pulses and geometric shaped metal contacts. The current pulses react with the... | 09/26/1989 |
| 4820657 | Method for altering characteristics of junction semiconductor devices Method for altering an electrical characteristic of a circuit having at least one junction formed from a first and a second semiconductor material involves applying at least one pulse --a voltage pulse, a current pulse, an energy pulse, or a power pulse a... | 04/11/1989 |
| 4747076 | Method of writing information into a fuse-type ROM Fuse-type ROM are provided with fuses which are formed on an insulating film, connected to conductor lines, and covered by a protective film. In order to write information into the fuse-type ROMs a ramp voltage is applied to the fuses so as to selectively... | 05/24/1988 |
| 4683442 | Operational amplifier circuit utilizing resistors trimmed by metal migration A method for trimming a diffused or implanted resistor located within an integrated circuit is disclosed. This technique for trimming a resistor requires the use of high current pulses and geometric shaped metal contacts. The current pulses react with the... | 07/28/1987 |
| 4661370 | Electric discharge processing of thin films A deposited film is processed in a preselected pattern by discharging electric energy through the film across a gas dielectric. In a preferred embodiment, a voltage pulse chain is applied to a moving probe spaced a preselected distance from the film. The ... | 04/28/1987 |
| 4646427 | Method of electrically adjusting the zener knee of a lateral polysilicon zener diode In a method of electrically altering the characteristics of a semiconductor device, a lateral polysilicon zener diode's zener knee voltage may be shifted either to a higher or lower voltage. An electrical potential may be applied in the forward direction ... | 03/03/1987 |
| 4606781 | Method for resistor trimming by metal migration A method for trimming a diffused or implanted resistor located within an integrated circuit is disclosed. This technique for trimming a resistor requires the use of high current pulses and geometric shaped metal contacts. The current pulses react with the... | 08/19/1986 |
| 4569120 | Method of fabricating a programmable read-only memory cell incorporating an antifuse utilizing ion implantation In fabricating a PROM cell, an electrical isolation mechanism (44 and 32) is formed in a semiconductive body to separate islands of an upper zone (36) of first type conductivity (N) in the body. A semiconductor is introduced into one of the islands to pro... | 02/11/1986 |
| 4534100 | Electrical method of making conductive paths in silicon A method of forming an electrical conductive path between parallel surfaces of a substrate is disclosed wherein a pulsed voltage, non-current limited, power supply causes aluminum to electromigrate between at least two opposing points to form an alloy wit... | 08/13/1985 |
| 4494302 | Accelerated annealing of gallium arsenide solar cells A method is provided for accelerating and improving the recovery of GaAs solar cells from the damage which they experience in space under high energy particle irradiation such as electrons, protons and neutrons. The method comprises combining thermal anne... | 01/22/1985 |
| 4420497 | Method of detecting and repairing latent defects in a semiconductor dielectric layer Defects in dielectric layers exhibiting low dielectric strength on silicon substrates (11) are deliberately damaged during manufacture to allow their repair by the formation of dielectric plugs (13B). The defects are damaged by the application of an elect... | 12/13/1983 |
| 4398343 | Method of making semi-amorphous semiconductor device A semi-amorphous semiconductor device manufacturing method in which a non-single crystal semiconductor layer is provided on a substrate to form therebetween a PN, PIN, PI or NI junction and a current is applied to the non-single crystal semiconductor laye... | 08/16/1983 |
| 4395293 | Accelerated annealing of gallium arsenide solar cells A method is provided for accelerating and improving the recovery of GaAs solar cells from the damage which they experience in space under high energy particle irradiation scuh as electrons, protons and neutrons. The method comprises combining thermal anne... | 07/26/1983 |
| 4210996 | Trimming method for resistance value of polycrystalline silicon resistors especially used as semiconductor integrated circuit resistors Current having a density higher than a critical value is passed through a polycrystalline resistor doped with impurities at a concentration higher than a critical value to decreasingly correct the initial value of the resistance, thereby trimming the resi... | 07/08/1980 |
| 4193003 | Method for controlling the migration of a chemical species within a solid substrate The method for controlling the migration of an electronegative chemical species within a solid substrate which exhibits ionic conduction consists in irradiating the substrate with electrons which have sufficient energy to penetrate into the substrate and ... | 03/11/1980 |
| 4174521 | PROM electrically written by solid phase epitaxy A memory cell, having a doped amorphous silicon layer, is formed on a thin layer of silicon alloy which is on a single crystal silicon substrate. The cell is programmed by applying a voltage between a surface contact and the substrate to cause a crystal c... | 11/13/1979 |
| 4131524 | Manufacture of semiconductor devices A method of manufacturing a semiconductor device comprising the steps of providing a plate-shaped semiconductor body, removing by spark erosion a first portion of the semiconductor body, and then using a selective etching process to remove only a second p... | 12/26/1978 |
| 4013485 | Process for eliminating undesirable charge centers in MIS devices The electrical properties of MIS semiconductor devices, which have been damaged by radiation, are restored by treating the devices in a properly oriented RF field at low pressure.... | 03/22/1977 |
| 4005523 | Semiconductor devices A process for the production of p-n junctions which comprises preparing a suitable silicon type-n crystal of 100Ω/cm to several kΩ/cm with the orientation (111), (112) and (110), heating the crystal to a temperature of between 700° C and 800° C, and a... | 02/01/1977 |
| 3999282 | Method for manufacturing semiconductor devices having oxide films and the semiconductor devices manufactured thereby A silicon crystal body having a major surface lying parallel to a {110} or {100} crystal plane is prepared. A silicon oxide film is formed on the major surface by heating the body in an atmosphere containing steam. Then, an aluminum layer is formed on the... | 12/28/1976 |
