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| Number | Title | Issue Date |
| 7443002 | Encapsulated microstructure and method of producing one such microstructure A microstructure including in a first layer insulated from a substrate by an insulator layer at least one sensitive element connected to at least one contact pad by an electrical connection and protected by a package cap. The sensitive element, the electrical connec... | 10/28/2008 |
| 7432208 | Method of manufacturing suspension structure A method of manufacturing a suspension structure including providing a substrate, forming a first photoresist pattern on the substrate, heating the first photoresist pattern to harden it as a sacrificial layer, forming a second photoresist pattern on the substrate a... | 10/07/2008 |
| 7432136 | Transistors with controllable threshold voltages, and various methods of making and operating same In one illustrative embodiment, the method comprises providing an SOI substrate comprised of an active layer, a buried insulation layer and a bulk substrate, the active layer being doped with a first type of dopant material, the bulk substrate having an inner well f... | 10/07/2008 |
| 7432173 | Methods of fabricating silicon-on-insulator substrates having a laser-formed single crystalline film In some methods of fabricating a silicon-on-insulator substrate, a semiconductor substrate is provided that includes a single crystalline structure within at least a defined region thereof. A first insulating film is formed on the defined region of the semiconductor... | 10/07/2008 |
| 7422943 | Semiconductor device capacitors with oxide-nitride layers and methods of fabricating such capacitors Capacitors having upper electrodes that include a lower electrode, a dielectric layer and an upper electrode that includes a conductive metal nitride layer and a doped polysilicon germanium layer are provided. At least part of the conductive metal nitride layer is o... | 09/09/2008 |
| 7422634 | Three inch silicon carbide wafer with low warp, bow, and TTV A high quality single crystal wafer of SiC is disclosed. The wafer has a diameter of at least about 3 inches, a warp of less than about 5 μm, a bow less than about 5 μm, and a total thickness variation of less than about 2.0 μm. ... | 09/09/2008 |
| 7416987 | Semiconductor device and method of fabricating the same According to the present invention, there is a provided a semiconductor device fabrication method having, forming a mask material in a surface portion of a semiconductor substrate, and forming a step having a projection by using the mask material; forming a dielectr... | 08/26/2008 |
| 7410854 | Method of making FUSI gate and resulting structure Generally disclosed is a method of a device comprising forming a polysilicon stack including a first and a second polysilicon layer with an intervening etch stop layer, wherein the first polysilicon layer height is at least one third a height of the polysilicon stac... | 08/12/2008 |
| 7410877 | Method for manufacturing SIMOX wafer and SIMOX wafer A method for manufacturing a SIMOX wafer includes: heating a silicon wafer, implanting oxygen ions so as to form a high oxygen concentration layer; implanting oxygen ions into the silicon wafer obtained by the forming of the high oxygen concentration layer to form a... | 08/12/2008 |
| 7393730 | Coplanar silicon-on-insulator (SOI) regions of different crystal orientations and methods of making the same In a first aspect, a first method is provided for semiconductor device manufacturing. The first method includes the steps of (1) providing a substrate; and (2) forming a first silicon-on-insulator (SOI) region having a first crystal orientation, a second SOI region ... | 07/01/2008 |
| 7384860 | Method of manufacturing a semiconductor device The present invention relates to a method of manufacturing a semiconductor device having an excellent gettering effect. In this method, when phosphorus is added to a poly-Si film, which has been crystallized by the addition of a metal, to subject the resultant poly-... | 06/10/2008 |
| 7368359 | Method for manufacturing semiconductor substrate and semiconductor substrate A semiconductor substrate (100) is acquired by forming a mask with a target thickness on a major surface of a single-crystal silicon substrate, implanting oxygen ions to the major surface at a high temperature, forming a surface protection layer for blocking ... | 05/06/2008 |
| 7361538 | Transistors and methods of manufacture thereof Transistors and methods of manufacture thereof are disclosed. A workpiece is provided, a gate dielectric is formed over the workpiece, and a gate is formed over the gate dielectric by exposing the workpiece to a precursor of hafnium (Hf) and a precursor of silicon (... | 04/22/2008 |
| 7361539 | Dual stress liner A semiconductor device structure is provided which includes a first field effect transistor (“FET”) having a first channel region, a first source region, a first drain region and a first gate conductor overlying the first channel region. A second FET is included... | 04/22/2008 |
| 7358124 | Thin film transistor array panel and manufacturing method thereof A TFT array panel includes: first and second gate members connected to each other; a gate insulating layer formed on the first and the second gate members; first and second semiconductor members formed on the gate insulating layer opposite the first and the second g... | 04/15/2008 |
| 7348648 | Interconnect structure with a barrier-redundancy feature An interconnect structure that includes a barrier-redundancy feature which is capable of avoiding a sudden open circuit after an electromigration (EM) failure as well as a method of forming the same are provided. In accordance with the present invention, the barrier... | 03/25/2008 |
| 7344933 | Method of forming device having a raised extension region A method is disclosed of forming an extension region for a transistor having a gate structure overlying a compound semiconductor layer. An anneal is used either before or after deep source/drain implantation to diffuse a dopant from a raised region adjacent the gate... | 03/18/2008 |
| 7323370 | SOI device with reduced junction capacitance An SOI FET comprising a silicon substrate having silicon layer on top of a buried oxide layer having doped regions and an undoped region is disclosed. The doped region has a dielectric constant different from the dielectric constant of the doped regions. A body also... | 01/29/2008 |
| 7319061 | Method for fabricating electronic device In a method for fabricating an electronic device including a transistor with a drain extension structure, a correspondence between a size of a gate electrode of the transistor and ion implantation conditions or heat treatment conditions for forming the drain extensi... | 01/15/2008 |
| 7317226 | Patterned SOI by oxygen implantation and annealing Methods for forming a patterned SOI region in a Si-containing substrate is provided which has geometries of about 0.25 μm or less. Specifically, one method includes the steps of: forming a patterned dielectric mask on a surface of a Si-containing substrate, wherein... | 01/08/2008 |
| 7316943 | Method for manufacturing semiconductor apparatus having drain/source on insulator A method for manufacturing a semiconductor apparatus, comprises: forming a first semiconductor layer on a semiconductor substrate of a transistor formation region; etching and removing a part of the fir... | 01/08/2008 |
| 7309634 | Non-volatile semiconductor memory devices using prominences and trenches A semiconductor substrate is patterned to form a depression and prominence. A floating gate is formed so as to cover at least both sidewalls of the prominence of the depression and prominence, and is then etched to form a trench for a device isolation self-aligned w... | 12/18/2007 |
| 7294552 | Electrical contact for a MEMS device and method of making A method for making a subsurface electrical contact on a micro-electrical-mechanical-systems (MEMS) device. The contact is formed by depositing a layer of polycrystalline silicon onto a surface within a cavity buried under a device silicon layer. The polycrystalline... | 11/13/2007 |
| 7288804 | Electrically programmable π-shaped fuse structures and methods of fabrication thereof Electrically programmable fuse structures for an integrated circuit and methods of fabrication thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first te... | 10/30/2007 |
| 7288458 | SOI active layer with different surface orientation A wafer having an SOI configuration and active regions having different surface orientations for different channel type transistors. In one example, semiconductor structures having a first surface orientation are formed on a donor wafer. Semiconductor structures hav... | 10/30/2007 |
| 7285471 | Process for transfer of a thin layer formed in a substrate with vacancy clusters Processes for forming semiconductor structure comprising a transfer layer transferred from a donor substrate are provided in which the resulting structure has improved quality with respect to defects and resulting structures therefrom. For example, a semiconductor o... | 10/23/2007 |
| 7282416 | Method for fabricating electronic device In a method for fabricating an electronic device including a transistor with a drain extension structure, a correspondence between a size of a gate electrode of the transistor and ion implantation conditions or heat treatment conditions for forming the drain extensi... | 10/16/2007 |
| 7271445 | Ultra-thin semiconductors bonded on glass substrates A method for forming a semiconductor on insulator structure includes providing a glass substrate, providing a semiconductor wafer, and performing a bonding cut process on the semiconductor wafer and the glass substrate to provide a thin semiconductor layer bonded to... | 09/18/2007 |
| 7268051 | Semiconductor on glass insulator with deposited barrier layer Methods and apparatus provide for: a silicon on insulator structure, comprising: a glass substrate; a layer of semiconductor material; and a deposited barrier layer of between about 60 nm to about 600 nm disposed between the glass substrate and the semiconductor mat... | 09/11/2007 |
| 7265420 | Semiconductor substrate layer configured for inducement of compressive or expansive force An integrated circuit (IC) utilizes a strained layer. The substrate can utilize trenches in a base layer to induce stress in a layer. The trenches define pillars on a back side of a bulk substrate or base layer of a semiconductor-on-insulator (SOI) wafer. ... | 09/04/2007 |
| 7265017 | Method for manufacturing partial SOI substrates There is closed a semiconductor device which comprises a semiconductor substrate including an SOI region where a first insulating film is buried, and a non-SOI region, the semiconductor substrate being provided with a boundary region formed between the SOI region an... | 09/04/2007 |
| 7262486 | SOI substrate and method for manufacturing the same The SOI substrate 1 has a supporting substrate 10, an insulating layer 20 formed on the supporting substrate 10 and a silicon layer 30 formed on the insulating layer 20. A through electrode 40 is provided in a device ... | 08/28/2007 |
| 7253035 | Thin film transistor array panel and manufacturing method thereof A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; forming a gate insulating layer; forming a semiconductor layer; forming a lower data line; forming an upper data line including a source ele... | 08/07/2007 |
| 7244991 | Semiconductor integrated device A semiconductor integrated apparatus, including: an SOI (Silicon On Insulator) substrate which has a support substrate and an embedded insulation film; an NMOSFET, a PMOSFET and an FBC (Floating Body Cell) formed on the SOI substrate separately from each other; a p ... | 07/17/2007 |
| 7202123 | Mesa isolation technology for extremely thin silicon-on-insulator semiconductor devices Silicon-on-insulator (SOI) structures with silicon layers less than 20 nm in thickness are used to form extremely thin silicon-on-insulator (ETSOI) semiconductor devices. ETSOI semiconductor devices can be efficiently manufactured by mesa isolation techniques. A met... | 04/10/2007 |
| 7186597 | Method of manufacturing transistors A mask is formed selectively on a crystalline silicon film containing a catalyst element, and an amorphous silicon film is formed so as to cover the mask. Phosphorus is implanted into the amorphous silicon film and the portion of the crystalline silicon film which i... | 03/06/2007 |
| 7183177 | Silicon-on-insulator wafer transfer method using surface activation plasma immersion ion implantation for wafer-to-wafer adhesion enhancement A method of fabricating a semiconductor-on-insulator structure from a pair of semiconductor wafers, includes forming an oxide layer on at least a first surface of a first one of the wafers and performing a bonding enhancement implantation step by ion implantation of... | 02/27/2007 |
| 7176102 | Method for producing SOI wafer and SOI wafer A method for producing an SOI wafer by the hydrogen ion delamination method comprising at least a step of bonding a base wafer and a bond wafer having a micro bubble layer formed by gas ion implantation and a step of delaminating a wafer having an SOI layer at the m... | 02/13/2007 |
| 7122865 | SOI wafer and process for producing it An SOI wafer, includes a substrate made from silicon, an electrically insulating layer with a thermal conductivity of at least 1.6 W/(Km) and a single-crystal silicon layer with a thickness of from 10 nm to 10 μm, a standard deviation of at most 5% from the mean la... | 10/17/2006 |
| 7102181 | Structure and method for dual-gate FET with SOI substrate A method of forming a dual gate fin-type field effect transistor (FinFET) structure patterns silicon fins over an insulator and patterns a gate conductor at an angle to the fins. The gate conductor is formed laterally adjacent to and over center portions of the fins... | 09/05/2006 |
