Class 257/E21.316 - Doping polycrystalline or amorphous silicon layer (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.315. This
No. of patents: 192
Last issue date: 10/21/2008

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Number	Title	Issue Date
7439116	Apparatus and method for forming polycrystalline silicon thin film Apparatus and method for forming a polycrystalline silicon thin film by converting an amorphous silicon thin film into the polycrystalline silicon thin film using a metal are provided. The method includes: a metal nucleus adsorbing step of introducing a vapor phase ...	10/21/2008
7439088	Liquid crystal display device and fabricating method thereof An array substrate for a liquid crystal display device includes a substrate, a gate line and a data line crossing each other to define a pixel region, a thin film transistor at a crossing of the gate and data lines, a metal pattern over the gate line, a passivation ...	10/21/2008
7393765	Low temperature CVD process with selected stress of the CVD layer on CMOS devices Device-enhancing coatings are deposited on CMOS devices by successively masking with photoresist each one of the sets of N-channel and P-channel devices while unmasking or leaving unmasked the other set, and after each step of successively masking one of the sets of...	07/01/2008
7361577	Method of manufacturing semiconductor device In a step of doping a silicon-based semiconductor film as a TFT active layer such as channel doping or the like, a protective film is formed by a CVD method as a pretreatment so as to prevent the silicon-based semiconductor film from being contaminated and etched. H...	04/22/2008
7312137	Transistor with shallow germanium implantation region in channel A transistor and a structure thereof, wherein a very shallow region having a high dopant concentration of germanium is implanted into a channel region of a transistor at a low energy level, forming an amorphous germanium implantation region in a top surface of the w...	12/25/2007
7303995	Method for reducing dimensions between patterns on a photoresist A semiconductor manufacturing method that includes providing a substrate, providing a layer of material over the substrate, providing a layer of photoresist over the material layer, patterning and defining the photoresist layer, depositing a layer of polymer over th...	12/04/2007
7268065	Methods of manufacturing metal-silicide features A method of manufacturing a microelectronic device including forming an opening in a dielectric layer located over a substrate, forming a semi-conductive layer substantially conforming to the opening, and forming a conductive layer substantially conforming to the se...	09/11/2007
7223676	Very low temperature CVD process with independently variable conformality, stress and composition of the CVD layer A low temperature process for depositing a coating containing any of silicon, nitrogen, hydrogen or oxygen on a workpiece includes placing the workpiece in a reactor chamber facing a processing region of the chamber, introducing a process gas containing any of silic...	05/29/2007
7220647	Method of cleaning wafer and method of manufacturing gate structure A method of cleaning a wafer, adapted for a patterned gate structure. The gate structures comprise a gate dielectric layer, a nitrogen-containing barrier layer and a silicon-containing gate layer sequentially stacked over the substrate. The method includes cleaning ...	05/22/2007
7192854	Method of plasma doping A method of plasma doping in which dilution of B2H6 is maximized for enhanced safety and stable plasma generation and sustention can be carried out without lowering of doping efficiency and in which the amount of dopant injected can be easily c...	03/20/2007
7094670	Plasma immersion ion implantation process A method of performing plasma immersion ion implantation on a workpiece in a plasma reactor chamber, includes placing the workpiece on a workpiece support in the chamber, controlling a temperature of the wafer support near a constant level, performing plasma immersi...	08/22/2006
7084000	Solid-state imaging device and method for manufacturing the same A solid-state imaging device according to the present invention includes a semiconductor substrate; a photoelectric conversion portion formed on the semiconductor substrate; a gate insulating film formed on the semiconductor substrate and covering the photoelectric ...	08/01/2006
6855605	Semiconductor device with selectable gate thickness and method of manufacturing such devices A method of forming layers, in the same device material, with different thickness or layer height in a semiconductor device comprises forming device material layer or gate electrode layer disposable parts in selected regions of the device layer. The disposable parts...	02/15/2005
6693022	CVD method of producing in situ-doped polysilicon layers and polysilicon layered structures Doped polysilicon layers and layered polysilicon structures are produced, and the layers and layered structures are structured. The doping is distinguished by the fact that the doping compound is added as a process gas during the chemical vapor deposition...	02/17/2004
6677211	Method for eliminating polysilicon residue A method for eliminating polysilicon residue is provided by converting the polysilicon residue into silicon nitride in two steps. A tilted ion implantation step is performed to implant nitrogen ions into the polysilicon residue to rich nitrogen containing...	01/13/2004
6660586	Semiconductor device and process for manufacturing same A process for manufacturing a semiconductor device includes the following steps applied to a semiconductor substrate having, on its main surface, a plurality of separation oxide films, formed in stripes parallel to each other, and gate oxide films formed ...	12/09/2003
6635310	Method of heat treatment A thermal processing method of the invention includes; a loading step of loading an object to be processed into a processing container, the object having a surface provided with a silicon film having a minutely irregular profile; and a doping step of intr...	10/21/2003
6596605	Method of forming germanium doped polycrystalline silicon gate of MOS transistor and method of forming CMOS transistor device using the same A method of forming polycrystalline silicon germanium gate electrode is disclosed. The method include the steps of forming gate insulation layer on a substrate, forming a polycrystalline silicon layer on the gate insulation layer and making a plasma dopin...	07/22/2003
6479373	Method of structuring layers with a polysilicon layer and an overlying metal or metal silicide layer using a three step etching process with fluorine, chlorine, bromine containing gases Doped polysilicon layers and layered polysilicon structures are produced, and the layers and layered structures are structured. The doping is distinguished by the fact that the doping compound is added as a process gas during the chemical vapor deposition...	11/12/2002
6468888	Method for forming polysilicon-germanium gate in CMOS transistor and device made thereby A method for making a ULSI MOSFET chip includes forming transistor gates on a substrate and a semiconductor device thereby made. The gates are formed by depositing a polysilicon layer on the substrate, implanting germanium into the polysilicon layer at a ...	10/22/2002
6372588	Method of making an IGFET using solid phase diffusion to dope the gate, source and drain A method of making an IGFET using solid phase diffusion is disclosed. The method includes providing a device region in a semiconductor substrate, forming a gate insulator on the device region, forming a gate on the gate insulator, forming an insulating la...	04/16/2002
6274467	Dual work function gate conductors with self-aligned insulating cap A dual work function gate conductor with a self-aligned insulating cap and method for forming the same is provided. Two diffusion regions are formed in a substrate and a gate stack is formed over the substrate between the diffusion regions. The gate stack...	08/14/2001
6214684	Method of forming a semiconductor device using an excimer laser to selectively form the gate insulator To form a high-quality insulating layer at a low temperature, a semiconductor layer is formed on an insulating surface of an insulating substrate, and the semiconductor layer is selectively modified by an excimer laser irradiated from a surface opposing t...	04/10/2001
6180499	Method for forming polysilicon-germanium gate in CMOS transistor and device made thereby A method for making a ULSI MOSFET chip includes forming transistor gates on a substrate. The gates are formed by depositing a polysilicon layer on the substrate, implanting germanium into the polysilicon layer at a comparatively low dose, and then oxidizi...	01/30/2001
6140159	Method for activating an ohmic layer for a thin film transistor An ohmic layer of CMOS TFT is activated at temperature less than 550° C. by doping N-type and P-type dopants into polycrystal semiconductor to form CMOS thin film transistor and then implanting hydrogen ions into CMOS thin film transistor into which the ...	10/31/2000
6087248	Method of forming a transistor having thin doped semiconductor gate A method of forming a transistor is disclosed that comprises the step forming a gate insulator layer 12 on an outer surface of the substrate 10. A first gate conductor layer 22 is formed outwardly from the gate insulator layer 12. The first gate conductor...	07/11/2000
6060375	Process for forming re-entrant geometry for gate electrode of integrated circuit structure A crystalline semiconductor gate electrode having a re-entrant geometry and a process for making same are disclosed. The novel gate electrode may be formed from a polysilicon layer on a substrate by first implanting a masked polysilicon layer with a neutr...	05/09/2000
5952721	Semiconductor device having oxygen-doped silicon layer so as to restrict diffusion from heavily doped silicon layer A phosphorous doped amorphous silicon storage node electrode is treated with heat so as to be converted into a phosphorous doped polysilicon storage electrode, and the heat causes the phosphorous to be diffused into a shallow n-type source region of an n-...	09/14/1999
5940733	Method of making polysilicon/tungsten silicide multilayer composite on an integrated circuit structure Described is an improved polysilicon/tungsten silicide (WSix) composite layer formed over an integrated circuit structure on a semiconductor wafer and characterized by improved step coverage and non tungsten-rich tungsten:silicon ratio of the W...	08/17/1999
5895259	Polysilicon diffusion doping method employing a deposited doped oxide layer with a highly uniform thickness A polysilicon diffusion doping method which employs a deposited dopant-rich oxide layer with a highly uniform distribution of dopant atoms and thickness. Polysilicon layers 1,500 angstroms thick have been doped, achieving average resistance values of 60 o...	04/20/1999
5888867	Non-uniform threshold voltage adjustment in flash eproms through gate work function alteration Aspects for forming a Flash EPROM cell with an adjustable threshold voltage are described. In a method aspect, the method includes forming a substrate structure to establish a foundation for cell formation, and forming a gate structure with a floating gat...	03/30/1999
5885869	Method for uniformly doping hemispherical grain polycrystalline silicon A method is disclosed for uniformly doping HSG polycrystalline silicon independent of the other layers of the semiconductor substrate. A semiconductor substrate having a silicon dioxide layer formed superjacent a polysilicon layer is provided in a chamber...	03/23/1999
5883000	Circuit device interconnection by direct writing of patterns therein An apparatus and method wherein conductive patterns are written in amorphous silicon or polysilicon deposited on an integrated circuit and used for interconnecting circuit elements contained therein. The substantially pure amorphous silicon or polysilicon...	03/16/1999
5874352	Method of producing MIS transistors having a gate electrode of matched conductivity type A method of producing an MIS transistor by preparing a substrate formed with a gate electrode and a semiconductor layer which defines a source region and a drain region, removing a natural oxide film from a surface of the gate electrode and from a surface...	02/23/1999
5798280	Process for doping hemispherical grain silicon A process for doping hemispherical grain silicon is provided and includes the steps of providing hemispherical grain silicon and a source of a dopant material and exposing the hemispherical grain silicon to the dopant material at a temperature less than t...	08/25/1998
5783257	Method for forming doped polysilicon films A number of wafers are loaded into a reaction vessel on a wafer boat; monosilane gas, phosphine gas and N2 O gas are supplied to form amorphous silicon film doped with, e.g., phosphorus; and then the wafers are annealed in, e.g., a different re...	07/21/1998
5739590	Semiconductor device having improved surface evenness A semiconductor device is constructed to have an insulating layer containing an impurity provided upon a semiconductor substrate. This insulating layer contains a plurality of windows of different sizes. A first layer is provided in the windows. This firs...	04/14/1998
5721150	Use of silicon for integrated circuit device interconnection by direct writing of patterns therein An apparatus and method wherein conductive patterns are written in amorphous silicon or polysilicon deposited on an integrated circuit and used for interconnecting circuit elements contained therein. The substantially pure amorphous silicon or polysilicon...	02/24/1998
5712176	Doping of silicon layers A process for forming a P2 O5 layer suitable for diffusion doping polysilicon gates is disclosed. The inventive process has a reduced thermal budget and helps to eliminate subsequent gate oxide roughness....	01/27/1998
5654209	Method of making N-type semiconductor region by implantation A semiconductor device at least including a region which contains a first impurity constituted by a group V element and a second impurity constituted by an element of high electronegativity or a halogen element such as Ti, Cl, O, Br, S, I or N in amorphou...	08/05/1997

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Class 257/E21.316 - Doping polycrystalline or amorphous silicon layer (EPO)