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An armor with rollers is provided that enables a user to move in all positions by rolling on a hard and smooth surface while constantly varying his bearing points on the ground.
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| Number | Title | Issue Date |
| 7413963 | Method of edge bevel rinse A method of edge bevel rinse. First, a wafer having a coating material layer disposed thereon is provided. A light beam is optically projected on the wafer to form a reference pattern. The reference pattern defines a central region, and a bevel region surrounding th... | 08/19/2008 |
| 7413960 | Method of forming floating gate electrode in flash memory device A method of forming a floating gate electrode in a flash memory device. The method includes forming an isolation film in an inactive region so that a step with a predetermined thickness can be generated between an active region and the inactive region, which are def... | 08/19/2008 |
| 7399703 | Process for patterning nanocarbon material, semiconductor device, and method for manufacturing semiconductor device A process for patterning a nanocarbon material includes a step of forming a nanocarbon layer on a substrate; a step of forming a first metal layer on the nanocarbon layer to pattern the first metal layer, the first metal layer containing at least one selected from t... | 07/15/2008 |
| 7351666 | Layout and process to contact sub-lithographic structures An integrated circuit and method for fabrication includes first and second structures, each including a set of sub-lithographic lines, and contact landing segments connected to at least one of the sub-lithographic lines at an end portion. The first and second struct... | 04/01/2008 |
| 7341960 | Method for making a metal oxide semiconductor device A method for making a MOS device includes: forming a titanium dioxide film on a semiconductor substrate; and subjecting the titanium dioxide film to a fluorine-containing ambient, and conducting passivation of grain boundary defects of the titanium dioxide film thro... | 03/11/2008 |
| 7271022 | Process for forming microstructures The present invention relates to a process for forming microstructures on a substrate. A plating surface is applied to a substrate. A first layer of photoresist is applied on top of the plating base. The first layer of photoresist is exposed to radiation in a patter... | 09/18/2007 |
| 6703297 | Method of removing inorganic gate antireflective coating after spacer formation Various methods of manufacturing are disclosed. In one aspect, a method of manufacturing is provided that includes forming an anti-reflective coating on a structure on a substrate. A first spacer and a second spacer are formed adjacent to the structure. T... | 03/09/2004 |
| 6703304 | Dual damascene process using self-assembled monolayer and spacers A method of fabricating a trench on an integrated circuit having first and second insulative layers includes providing a layer of material over the insulative layers; forming a first self-assembled monolayer on the layer of material; etching the first sel... | 03/09/2004 |
| 6699792 | Polymer spacers for creating small geometry space and method of manufacture thereof In forming an opening or space in a substrate, a layer of photoresist is provided on the substrate, and the photoresist is patterned to provide photoresist bodies having respective adjacent sidewalls. A polymer layer is provided on the resulting structure... | 03/02/2004 |
| 6692648 | Method of plasma heating and etching a substrate We have discovered a method of reducing the effect of material sputtered/etched during the preheating of a substrate. One embodiment of the method pertains to the preheating of a substrate which includes a material which is to be pattern etched at a tempe... | 02/17/2004 |
| 6690077 | Antireflective coating and field emission display device, semiconductor device and wiring line comprising same Titanium aluminum nitrogen ("Ti--Al--N") is deposited onto a semiconductor substrate area to serve as an antireflective coating. For wiring line fabrication processes, the Ti--Al--N layer serves as a cap layer which prevents unwanted reflection of photoli... | 02/10/2004 |
| 6686289 | Method for minimizing variation in etch rate of semiconductor wafer caused by variation in mask pattern density In a method for minimizing a variation in an etch rate of a semiconductor wafer caused by a variation in a mask pattern density, the method includes determining a reference amount of an etch gas for a reference mask pattern density, obtaining an optimized... | 02/03/2004 |
| 6682988 | Growth of photoresist layer in photolithographic process A method of fabricating a feature of an integrated circuit in a layer of material includes providing a layer of photoresist having a first thickness over the layer of material; forming apertures in the layer of photoresist; growing the layer of photoresis... | 01/27/2004 |
| 6682996 | Method for forming a semiconductor structure using a disposable hardmask A method is provided, which includes patterning a stack of layers spaced below a sacrificial hardmask layer. In some embodiments, the method may include patterning a lower hardmask layer arranged above the stack of layers. Such a patterning process may in... | 01/27/2004 |
| 6677227 | Method of forming patterned metalization on patterned semiconductor wafers A metalization process forms metal contacts having defined profiles for contact between microelectromechanical (MEMS) devices or chemical sensors with semiconductor devices. Gold contacts may be used for connecting the MEMS devices or chemical sensors to ... | 01/13/2004 |
| 6673719 | Method for etching using a multilevel hard mask A method for physical etching using a multilevel hard mask. A substrate having a multilayer structure thereon is provided. A BPSG layer, a masking material layer and a patterned photoresist layer are sequentially formed on the multilayer structure, wherei... | 01/06/2004 |
| 6673684 | Use of diamond as a hard mask material A method for producing an integrated circuit includes providing a diamond layer above a layer of conductive material. A cap layer is provided above the diamond layer and patterned to form a cap feature. The diamond layer is patterned according to the cap ... | 01/06/2004 |
| 6673685 | Method of manufacturing semiconductor devices A process for economical and efficient fabrication of gate electrodes no larger than 50 nm, which is beyond the limit of exposure, is characterized by gate-electrode trimming and mask trimming with high resist selectivity which are performed in combinatio... | 01/06/2004 |
| 6670262 | Method of manufacturing semiconductor device A method of manufacturing a semiconductor device which is capable of forming a gate structure having dimensions as designed. A silicon oxide film, a polysilicon film and a silicon oxide film are formed in the order named on a silicon substrate. Then, the ... | 12/30/2003 |
| 6667210 | Flash memory cell process using a hardmask A method is described for forming a memory structure using a hardmask (65). The hardmask (65) protects the second polysilicon layer (55) during a SAS etch process. In addition, sidewall structures (95) are formed which protect the inter-polysilicon dielec... | 12/23/2003 |
| 6667243 | Etch damage repair with thermal annealing A method of manufacturing a semiconductor device etches a feature on a substrate in accordance with a photoresist mask. The photoresist mask is removed by plasma etching. Laser thermal annealing is performed to vaporize polymer residue created during the ... | 12/23/2003 |
| 6664173 | Hardmask gate patterning technique for all transistors using spacer gate approach for critical dimension control An electrical element may be made by providing a hardmask unit that has a double gate stack with a first gate layer, a first hardmask layer formed over the first gate layer, a second gate layer formed over the first hardmask layer, and a second hardmask l... | 12/16/2003 |
| 6660647 | Method for processing surface of sample A surface processing method of a sample having a mask layer that does not contain carbon as a major component formed on a substance to be processed, the substance being a metal, semiconductor and insulator deposited on a silicon substrate, includes the st... | 12/09/2003 |
| 6656796 | Multiple etch method for fabricating split gate field effect transistor (FET) device Within a method for fabricating a split gate field effect transistor (FET) device there is employed a two step etch method for forming a floating gate electrode. Within the two step etch method there is employed a patterned first masking layer and a blank... | 12/02/2003 |
| 6653735 | CVD silicon carbide layer as a BARC and hard mask for gate patterning A BARC comprising materials having a lower pinhole density than that of silicon oxynitride and materials having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of polysilicon than that of amorphous carbon is emplo... | 11/25/2003 |
| 6653231 | Process for reducing the critical dimensions of integrated circuit device features A process for forming sub-lithographic features in an integrated circuit is disclosed herein. A process for enhancing the etch trimmability and the etch stability of features patterned on a photoresist layer is also disclosed herein. The process includes ... | 11/25/2003 |
| 6653028 | Photo mask for fabricating a thin film transistor liquid crystal display The present invention discloses a photo mask employing in a TFT-LCD fabrication using 4-mask process. The disclosed photo mask comprises a transparent substrate and a shielding pattern formed thereon, wherein the shielding pattern includes a pair of first... | 11/25/2003 |
| 6649532 | Methods for etching an organic anti-reflective coating One embodiment of the present invention is a process for etching an organic anti-reflective coating on a base of a substrate, the process including steps of: (a) placing the substrate into a processing chamber; (b) introducing into the processing chamber ... | 11/18/2003 |
| 6649525 | Methods and systems for controlling resist residue defects at gate layer in a semiconductor device manufacturing process Methods and systems are disclosed for reducing resist residue defects in a semiconductor manufacturing process. The methods comprise appropriate adjustment of hardware, substrate, resist, developer, and process variables in order to remove resist residues... | 11/18/2003 |
| 6646662 | Patterning method, patterning apparatus, patterning template, and method for manufacturing the patterning template A template 1 is brought close to or in contact with a surface to be patterned 111 and patterns are formed with liquid 62 on the surface 111. This method comprises the steps of: bringing the template 1 close to or essentially in contact with the surface 11... | 11/11/2003 |
| 6645851 | Method of forming planarized coatings on contact hole patterns of various duty ratios A method of forming a planarized photoresist coating on a substrate having holes with different duty ratios is described. A first photoresist preferably comprised of a Novolac resin and a diazonaphthoquinone photoactive compound is coated on a substrate a... | 11/11/2003 |
| 6645702 | Treat resist surface to prevent pattern collapse The present invention relates to systems and methods for increasing the hydrophobicity of patterned resists. In one embodiment, the present invention relates to a method of processing an ultra-thin resist, involving depositing the ultra-thin photoresist o... | 11/11/2003 |
| 6635528 | Method of planarizing a conductive plug situated under a ferroelectric capacitor An embodiment of the instant invention is a method of fabricating a planar conductive via in an opening through a dielectric layer having a top surface, a bottom surface and the opening having sides, the method comprising the steps of: depositing a first ... | 10/21/2003 |
| 6632115 | Method for forming transparent conductive film using chemically amplified resist A method for patterning an indium-tin-oxide (ITO) film by using a chemically amplified resist, causing no resist separation nor adhesion degradation even if the ITO film is exposed to white light after the resist development. An amorphous ITO film is form... | 10/14/2003 |
| 6630288 | Process for forming sub-lithographic photoresist features by modification of the photoresist surface A process for forming sub-lithographic features in an integrated circuit is disclosed herein. The process includes modifying a photoresist layer after patterning and development but before it is utilized to pattern the underlying layers. The modified phot... | 10/07/2003 |
| 6627971 | Polysilicon structures with different resistance values for gate electrodes, resistors, and capacitor plates A device with a plurality of structures with different resistance values is formed on a substrate. A polysilicon layer is formed upon the substrate. A silicon oxide layer is formed over the substrate. A hard masking layer is formed over the silicon oxide ... | 09/30/2003 |
| 6627524 | Methods of forming transistor gates; and methods of forming programmable read-only memory constructions The invention includes a method of forming a transistor gate. One or more conductive materials are formed over a semiconductor substrate, and a block is formed over the one or more conductive materials. The block comprises a photoresist mass and a materia... | 09/30/2003 |
| 6627557 | Semiconductor device and method for manufacturing the same Disclosed is a method of manufacturing a semiconductor device, which comprises the steps of forming an insulating film or a metal film on a surface of a semiconductor substrate, forming at least two kinds of mask on a surface of the insulating film or the... | 09/30/2003 |
| 6627360 | Carbonization process for an etch mask A method of forming an etch mask includes patterning a top surface of a photoresist layer, carbonizing the patterned top surface of the photoresist layer and selectively removing portions of the photoresist layer. Portions of the photoresist layer under t... | 09/30/2003 |
| 6624068 | Polysilicon processing using an anti-reflective dual layer hardmask for 193 nm lithography A lithographic method of forming submicron polysilicon features on a semiconductor substrate, including the steps of coating said substrate with an anti-reflective coating (ARC) comprising two layers having matched indices of refraction (n) and extinction... | 09/23/2003 |
