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| Number | Title | Issue Date |
| 7413963 | Method of edge bevel rinse A method of edge bevel rinse. First, a wafer having a coating material layer disposed thereon is provided. A light beam is optically projected on the wafer to form a reference pattern. The reference pattern defines a central region, and a bevel region surrounding th... | 08/19/2008 |
| 7341922 | Dry etching method, fabrication method for semiconductor device, and dry etching apparatus When etching is performed with respect to a silicon-containing material by using a dry etching apparatus having a dual power source, the application of bias power is initiated before oxidization proceeds at a surface of the silicon-containing material. Specifically,... | 03/11/2008 |
| 7122488 | High density plasma process for the formation of silicon dioxide on silicon carbide substrates Methods are provided for forming silicon dioxide (SiO2) on a silicon carbide (SiC) substrate. The method comprises: providing a SiC substrate; supplying an atmosphere including oxygen; performing a high-density (HD) plasma-based process; and, forming a SiO2 layer ov... | 10/17/2006 |
| 7051454 | Method for etching a metal layer in a semiconductor device A method for etching a metal layer on which an oxide-based ARC layer is coated in a semiconductor device comprises the step of performing a dry cleaning process by using a Cl2/CHF3 based gas, after dry cleaning the ARC layer by using the oxide-... | 05/30/2006 |
| 6703297 | Method of removing inorganic gate antireflective coating after spacer formation Various methods of manufacturing are disclosed. In one aspect, a method of manufacturing is provided that includes forming an anti-reflective coating on a structure on a substrate. A first spacer and a second spacer are formed adjacent to the structure. T... | 03/09/2004 |
| 6699795 | Gate etch process A method of making a semiconductor structure includes etching an anti-reflective coating layer at a pressure of 10 millitorr or less; etching a nitride layer with a first nitride etch plasma having a first F:C ratio; and etching the nitride layer with a s... | 03/02/2004 |
| 6696722 | Storage node of DRAM cell A storage node of a DRAM cell capacitor includes a first insulating layer in which a bit line pattern is formed, a second insulating layer formed on the first insulating layer of which material is different from that of the second insulating layer, a firs... | 02/24/2004 |
| 6693022 | CVD method of producing in situ-doped polysilicon layers and polysilicon layered structures Doped polysilicon layers and layered polysilicon structures are produced, and the layers and layered structures are structured. The doping is distinguished by the fact that the doping compound is added as a process gas during the chemical vapor deposition... | 02/17/2004 |
| 6686295 | Anisotropic etch method A method to anisotropically etch an oxide/silicide/poly sandwich structure on a silicon wafer substrate in situ, that is, using a single parallel plate plasma reactor chamber and a single inert cathode, with a variable gap between cathode and anode. This ... | 02/03/2004 |
| 6682996 | Method for forming a semiconductor structure using a disposable hardmask A method is provided, which includes patterning a stack of layers spaced below a sacrificial hardmask layer. In some embodiments, the method may include patterning a lower hardmask layer arranged above the stack of layers. Such a patterning process may in... | 01/27/2004 |
| 6673685 | Method of manufacturing semiconductor devices A process for economical and efficient fabrication of gate electrodes no larger than 50 nm, which is beyond the limit of exposure, is characterized by gate-electrode trimming and mask trimming with high resist selectivity which are performed in combinatio... | 01/06/2004 |
| 6667210 | Flash memory cell process using a hardmask A method is described for forming a memory structure using a hardmask (65). The hardmask (65) protects the second polysilicon layer (55) during a SAS etch process. In addition, sidewall structures (95) are formed which protect the inter-polysilicon dielec... | 12/23/2003 |
| 6667243 | Etch damage repair with thermal annealing A method of manufacturing a semiconductor device etches a feature on a substrate in accordance with a photoresist mask. The photoresist mask is removed by plasma etching. Laser thermal annealing is performed to vaporize polymer residue created during the ... | 12/23/2003 |
| 6660620 | Method of forming noble metal pattern A process for high resolution patterning of noble metals, such as platinum, for forming various semiconductor devices, such as capacitors or wiring patterns, is disclosed. A layer of noble metal, which will form an upper electrode of a capacitor, is forme... | 12/09/2003 |
| 6656847 | Method for etching silicon nitride selective to titanium silicide The invention provides a method for etching silicon nitride selective to titanium silicide and fabricating multi-level contact openings on a quartermicron device using a two step etch process. The process begins by providing a substrate having thereover a... | 12/02/2003 |
| 6653237 | High resist-selectivity etch for silicon trench etch applications Processes for forming trenches within silicon substrates are described. According to an embodiment of the invention, a masked substrate is initially provided that comprises (a) a silicon substrate and (b) a patterned resist layer over the silicon substrat... | 11/25/2003 |
| 6651678 | Method of manufacturing semiconductor device A method of etching a semiconductor device preventing tapering of a gate electrode edge includes a main etching of an electrode or wiring material supported by a dielectric film at a semiconductor substrate surface to expose the dielectric film. After the... | 11/25/2003 |
| 6645869 | Etching back process to improve topographic planarization of a polysilicon layer An etching back process to improve topographic planarization of a polysilicon layer. First, a polysilicon layer is formed to fill a contact hole between two adjacent insulating structures and cover the entire surface of a semiconductor substrate to a pred... | 11/11/2003 |
| 6646301 | Floating gate semiconductor device A semiconductor device has a floating gate having a side wall with a generally vertical upper section and a tapered lower section and a first insulation film formed on the side wall of the floating gate by thermal oxidation. The first insulation film has ... | 11/11/2003 |
| 6638813 | Method of forming a composite spacer to eliminate polysilicon stringers between elements in a pseudo SRAM cell A process for forming a composite insulator spacer on the sides of a buried stack capacitor structure, wherein the buried stack capacitor structure is located overlying a portion of an insulator filled, shallow trench isolation (STI) region, has been deve... | 10/28/2003 |
| 6635185 | Method of etching and cleaning using fluorinated carbonyl compounds A method comprising etching a material under plasma etching conditions using an etching composition which has a GWP of no greater than about 3000 and which comprises at least one etchant compound having a formula selected from the group consisting of F--C... | 10/21/2003 |
| 6635573 | Method of detecting an endpoint during etching of a material within a recess We have discovered a method of detecting the approach of an endpoint during the etching of a material within a recess such as a trench or a contact via. The method provides a clear and distinct inflection endpoint signal, even for areas of a substrate con... | 10/21/2003 |
| 6633072 | Fabrication method for semiconductor integrated circuit devices and semiconductor integrated circuit device To improve the shape of a gate electrode having SiGe, after patterning a gate electrode 15G having an SiGe layer 15b by a dry etching process, a plasma processing (postprocessing) is carried out in an atmosphere of an Ar/CHF3 gas. Thereby, the ... | 10/14/2003 |
| 6630405 | Method of gate patterning for sub-0.1 μm technology A method of gate patterning, including the following steps. A semiconductor structure having an upper silicon layer is provided. The semiconductor structure has a gate conductor region. A first gate oxide layer is formed over the semiconductor structure. ... | 10/07/2003 |
| 6627971 | Polysilicon structures with different resistance values for gate electrodes, resistors, and capacitor plates A device with a plurality of structures with different resistance values is formed on a substrate. A polysilicon layer is formed upon the substrate. A silicon oxide layer is formed over the substrate. A hard masking layer is formed over the silicon oxide ... | 09/30/2003 |
| 6624068 | Polysilicon processing using an anti-reflective dual layer hardmask for 193 nm lithography A lithographic method of forming submicron polysilicon features on a semiconductor substrate, including the steps of coating said substrate with an anti-reflective coating (ARC) comprising two layers having matched indices of refraction (n) and extinction... | 09/23/2003 |
| 6620575 | Construction of built-up structures on the surface of patterned masking used for polysilicon etch The present invention pertains to a method for depositing built-up structures on the surface of patterned masking material used for semiconductor device fabrication. Such built-up structures are useful in achieving critical dimensions in the fabricated de... | 09/16/2003 |
| 6613682 | Method for in situ removal of a dielectric antireflective coating during a gate etch process The present invention provides a method for the simultaneous removal of an oxygen and/or nitrogen-containing dielectric antireflective coating ("DARC") during plasma etching of an underlying layer in a film stack. According to the method of the invention,... | 09/02/2003 |
| 6593242 | Process for planarization and recess etching of integrated circuits The invention is directed to a process for forming a recess in at least one polysilicon overfilled trench in an integrated circuit. The process includes the following steps: uniformly etching the polysilicon overfill layer; stopping the etching before the... | 07/15/2003 |
| 6586145 | Method of fabricating semiconductor device and semiconductor device A method of fabricating a semiconductor device causing no pattern shifting of a peripheral oxide film etc. in removal of both of an antireflection film and a mask pattern and having a fine structure not implementable solely by photolithography and the sem... | 07/01/2003 |
| 6583063 | Plasma etching of silicon using fluorinated gas mixtures A method of etching silicon using a plasma generated from a gas comprising fluorine (F), oxygen (O), hydrogen (H) and carbon (C).... | 06/24/2003 |
| 6583065 | Sidewall polymer forming gas additives for etching processes A process of reducing critical dimension (CD) microloading in dense and isolated regions of etched features of silicon-containing material on a substrate uses a plasma of an etchant gas and an additive gas. In one version, the etchant gas comprises haloge... | 06/24/2003 |
| 6566272 | Method for providing pulsed plasma during a portion of a semiconductor wafer process A method for processing a semiconductor wafer with a plasma using continuous RF power for a first phase of wafer processing and with pulsed RF power for a second phase of wafer processing.... | 05/20/2003 |
| 6562722 | Method and apparatus for dry etching A method and apparatus for dry etching changes at least one of the effective pumping speed of a vacuum chamber and the gas flow rate to alter the processing of an etching pattern side wall of a sample between first and second conditions. The first and sec... | 05/13/2003 |
| 6551941 | Method of forming a notched silicon-containing gate structure A method of forming a notch silicon-containing gate structure is disclosed. This method is particularly useful in forming a T-shaped silicon-containing gate structure. A silicon-containing gate layer is etched to a first desired depth using a plasma gener... | 04/22/2003 |
| 6551942 | Methods for etching tungsten stack structures The invention encompasses methods for etching and/or over-etching tungsten stack structures, especially tungsten-polysilicon stack structures. The etching methods of the invention preferably employ a Cl2 /NF3 etchant, optionally incl... | 04/22/2003 |
| 6544896 | Method for enhancing etching of TiSix Conventional methods of etching TiSix use Cl2 or HBr as the plasma etchant. However, these methods can lead to undesirable residues, due to the presence of silicon nodules in the TiSix The present invention overcomes the r... | 04/08/2003 |
| 6544887 | Polycide etch process A method for etching contact openings into a polycide layer including a metal silicide layer and a polysilicon layer comprises providing a substrate that includes a polycide layer, forming a patterned photoresist mask, and etching with a series of plasmas... | 04/08/2003 |
| 6545308 | Funnel shaped structure in polysilicon Disclosed is a vertically oriented capacitor structure, which is of particular usefulness in MOS DRAM memory modules. The structure has upper and lower polysilicon capacitor plates separated by a dielectric layer, each of the plates and dielectric layers ... | 04/08/2003 |
| 6541164 | Method for etching an anti-reflective coating A method for etching and removing an anti-reflective coating from a substrate. The method comprises providing a substrate supporting a conductive layer (a tungsten-silicide layer) having an anti-reflective coating (e.g., a dielectric anti-reflective coati... | 04/01/2003 |
