Class 257/E21.309 - By liquid etching only (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.308. This subclass
No. of patents: 343
Last issue date: 09/23/2008

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Number	Title	Issue Date
7427545	Trench memory cells with buried isolation collars, and methods of fabricating same The present invention relates to semiconductor devices, preferably dynamic random access memory (DRAM) cells, each of which contains at least one trench capacitor with a buried isolation collar. The trench capacitor is located in a trench in a semiconductor substrat...	09/23/2008
7405165	Dual-tank etch method for oxide thickness control A dual-tank etch method which is suitable for the stripping of a silicon nitride layer from a pad oxide layer provided on a substrate, and etching of the pad oxide layer to a desired target thickness, is disclosed. The method includes providing a first processing ta...	07/29/2008
7381583	MEMS RF switch integrated process A capacitance coupled, transmission line-fed, radio frequency MEMS switch and its fabrication process using photoresist and other low temperature processing steps are described. The achieved switch is disposed in a low cost dielectric housing free of undesired elect...	06/03/2008
7358195	Method for fabricating liquid crystal display device In etching a metal line formed as a dual layer of aluminum alloy and molybdenum, the metal line consisting of the dual layer of aluminum alloy and molybdenum is etched through one-time wet etching by applying the etchant including HNO3, HClO4, ...	04/15/2008
7358196	Wet chemical treatment to form a thin oxide for high k gate dielectrics Described herein are methods of forming a thin silicon dioxide layer having a thickness of less than eight angstroms on a semiconductor substrate to form the bottom layer of a gate dielectric. A silicon dioxide layer having a thickness of less than eight angstroms m...	04/15/2008
7325299	Method of making a circuitized substrate A method of making a circuitized substrate. A conductive layer having a substantially planar upper surface is formed on and in direct mechanical contact with an upper surface of a substrate. A portion of the conductive layer is removed to form an interim side wall i...	02/05/2008
7309658	Molecular self-assembly in substrate processing Systems and methods for molecular self-assembly are provided. The molecular self-assembly receives a substrate that includes one or more regions of dielectric material. A molecularly self-assembled layer is formed on an exposed surface of the dielectric material. Th...	12/18/2007
7279411	Process for forming a redundant structure Device and method of fabricating device. The device includes a dual damascene line having a metal line and a via, and a redundant liner arranged to divide the metal line. The method includes forming a trench in a metal stripe of a dual damascene line, depositing a b...	10/09/2007
7214597	Electronic components and method of fabricating the same A method is provided for fabricating integrated electronic components. According to the method, an initial structure is produced on the surface of a first substrate. This initial structure incorporates a defined pattern formed from volumes of differentiated material...	05/08/2007
7208831	Semiconductor device having multilayer wiring structure and method, wherein connecting portion and wiring layer are formed of same layer A method for manufacturing a semiconductor device includes a step of forming a first groove in a first insulating film, forming a conductive film in the first groove, a step of selectively forming a second insulating film on the conductive film and the first insulat...	04/24/2007
7185428	Method of making a circuitized substrate A circuitized substrate and a method of making the circuitized substrate is provided. The circuitized substrate includes a substrate having a substantially planar upper surface and a conductive layer positioned on the substantially planar upper surface. The conducti...	03/06/2007
7105458	Method of etching semiconductor devices using a hydrogen peroxide-water mixture The present invention is a method of producing semiconductor devices and an etching liquid with which the titanium nitride film can be removed without thinning of the CoSi layer. A hydrogen peroxide-water mixture is used for removal of the titanium nitride film in t...	09/12/2006
6794270	Method for shallow trench isolation fabrication and partial oxide layer removal A method for forming thoroughly deposited shallow trench isolation. A first oxide layer is formed conformally over the surface of a semiconductor substrate and on a trench thereon with an aspect ratio greater than 3. A liquid etching shield is filled in the trench b...	09/21/2004
6703291	Selective NiGe wet etch for transistors with Ge body and/or Ge source/drain extensions The wet etch stage of the salicide process normally used to fabricate polysilicon and silicon-based semiconductor transistors may not be appropriate for germanium-based transistors because the wet etch chemicals at such temperatures will dissolve the germ...	03/09/2004
6699769	Method for fabricating capacitor using electrochemical deposition and wet etching Provided is a method for fabricating a capacitor using an electrochemical deposition method and Ce(NH4)2 (NO3)6 solution. The method includes the steps of: a) forming a contact hole in an insulation layer on a s...	03/02/2004
6695962	Anode designs for planar metal deposits with enhanced electrolyte solution blending and process of supplying electrolyte solution using such designs An anode assembly by which a solution can be supplied to a surface of a semiconductor substrate includes a housing defining an internal housing volume into which the solution can flow. A closure is provided for the internal housing volume, and the solutio...	02/24/2004
6695914	System for processing a workpiece An apparatus for processing a workpiece in a micro-environment includes a workpiece housing connected to a motor for rotation. The workpiece housing forms a processing chamber where one or more processing fluids are distributed across at least one face of...	02/24/2004
6696358	Viscous protective overlayers for planarization of integrated circuits The present invention relates to the planarization of surfaces as typically encountered in the fabrication of integrated circuits, particularly copper conductors and Ta/TaN barrier layers encountered in damascene and dual damascene interconnects. The pres...	02/24/2004
6693020	Method of preparing copper metallization die for wirebonding A method of preparing a semiconductor wafer having a integrated circuits formed on it that have pads formed of copper includes the steps of removing oxide from the copper pads and then the vacuum packing the wafer in a shock-proof container. The oxide may...	02/17/2004
6693003	Semiconductor device and manufacturing method of the same In a semiconductor device, formed are a lower capacitor electrode on an element isolation film on a silicon substrate, a capacitor insulating film and an upper capacitor electrode. A silicon oxide film is formed on the entire surface of the silicon substr...	02/17/2004
6692976	Post-etch cleaning treatment The present disclosure relates to a post-etch cleaning treatment for a semiconductor device such as a FeRAM. The treatment comprises providing an etchant comprising both a fluorine compound and a chlorine compound, and applying the etchant to the semicond...	02/17/2004
6693320	Capacitor structures with recessed hemispherical grain silicon Capacitor structures and capacitors with edge zones that are substantially free of hemispherical grain silicon along the upper edges of the capacitor structures are disclosed. The resulting recessed hemispherical grain silicon layers reduce or prevent sep...	02/17/2004
6692613	Reactor for processing a semiconductor wafer A method for processing a semiconductor wafer or similar article includes the step of spinning the wafer and applying a fluid to a first side of the wafer, while it is spinning. The fluid flows radially outwardly in all directions, over the first side of ...	02/17/2004
6693365	Local electrochemical deplating of alignment mark regions of semiconductor wafers Local electrochemical deplating of alignment mark regions of semiconductor wafers is disclosed. A tank holds an electrolytic solution. A primary cathode submersed within the solution is at least partially insulated therefrom. An electrochemically metal pl...	02/17/2004
6683009	Method for local etching A method is described for local etching of surfaces. The method includes the steps of providing a surface, providing an etchant, and providing a device for supplying and extracting the etchant. The device contains two cylindrical lines of different cross-...	01/27/2004
6683007	Etching and cleaning methods and etching and cleaning apparatus used therefor An etching/cleaning method makes it possible to effectively remove unnecessary materials on a semiconductor wafer, having a surface peripheral area and a surface device area, without damaging the device area. The semiconductor is rotated in a horizontal p...	01/27/2004
6680253	Apparatus for processing a workpiece A system for processing a workpiece includes a base having a bowl or recess for holding a liquid. A process reactor or head holds a workpiece between an upper rotor and a lower rotor. A head lifter lowers the head holding the workpiece into contact with t...	01/20/2004
6670274	Method of forming a copper damascene structure comprising a recessed copper-oxide-free initial copper structure A method of forming a planarized final copper structure including the following steps. A structure is provided having a patterned dielectric layer formed thereover. The patterned dielectric layer having an opening formed therein. A barrier layer is formed...	12/30/2003
6666922	System for processing a workpiece An apparatus for processing a workpiece in a micro-environment includes a workpiece housing connected to a motor for rotation. The workpiece housing forms a substantially closed processing chamber where one or more processing fluids are distributed across...	12/23/2003
6664195	Method for forming damascene metal gate The present invention relates to a method of forming a damascene gate electrode of highly integrated MOS transistor capable of easily removing a dummy polysilicon layer. The disclosed comprises the steps of forming a dummy gate insulating layer and a poly...	12/16/2003
6664197	Process for etching thin-film layers of a workpiece used to form microelectronic circuits or components A process for removing at least one thin-film layer from a surface of a workpiece pursuant to manufacturing a microelectronic interconnect or component is set forth. Generally stated, the process comprises the oxidation of at least a portion of the at lea...	12/16/2003
6664128	Bump fabrication process The present invention provides a bump fabrication process. After forming an under bump metallurgy (UBM) layer and bumps in sequence over the substrate, the under bump metallurgy layer that is not covered by the bumps is etched with an etchant. The etchant...	12/16/2003
6660098	System for processing a workpiece An apparatus for processing a workpiece in a micro-environment includes a workpiece housing connected to a motor for rotation. The workpiece housing defines a substantially closed processing chamber therein in which one or more processing fluids are distr...	12/09/2003
6661048	Semiconductor memory device having self-aligned wiring conductor According to the present invention, an overlay margin is secured for matching a wiring electrode 11 with a storage electrode 15 of a capacitor at their point of contact and the required area for a memory cell can be decreased by placing the plug electrode...	12/09/2003
6653229	Integrated circuit with a recessed conductive layer An improved method for making an integrated circuit. That method includes forming a first dielectric layer on a substrate, etching a trench into that layer, then filling the trench with a conductive material. The conductive material is then electropolishe...	11/25/2003
6652981	Etching process for making electrodes Substantially transparent electrodes are formed on a substrate by a process including forming on the substrate, in order, a bottom high index layer, a metallic conductive layer, and a top high index layer with a conductivity of at least about 400 Ω/squar...	11/25/2003
6649513	Copper back-end-of-line by electropolish A method of fabricating a planarized metal structure comprising the following steps. A structure is provided. A patterned dielectric layer is formed over the structure. The patterned dielectric layer having an opening formed therein and exposing at least ...	11/18/2003
6645807	Method for manufacturing semiconductor device After a metal layer is formed on a dielectric film, the metal layer is subjected to an oxidation process using a liquid having oxidizing power, thereby forming an adhesion layer. Then, an electrode or wiring is formed on the adhesion layer....	11/11/2003
6645875	Method of processing metal and method of manufacturing semiconductor device using the metal When a barrier metal disposed on a thin film resistor material is wet-etched to expose the underlying thin film resistor material as a thin film resistor, the wet etching is performed at first and second steps. The first step is performed using H2	11/11/2003
6635565	Method of cleaning a dual damascene structure A method of cleaning a dual damascene structure includes forming a first conductive layer in a substrate. A dielectric layer is formed over the substrate. A dual damascene opening is formed in the dielectric layer to expose the first conductive layer. A H...	10/21/2003

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Class 257/E21.309 - By liquid etching only (EPO)