Class 257/E21.305 - Physical or chemical etching of layer, e.g., to produce a patterned layer from pre-deposited extensive layer (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.3 This subclass
No. of patents: 40
Last issue date: 10/28/2008

Number	Title	Issue Date
7442644	Method for manufacturing nitride semiconductor wafer or nitride semiconductor device; nitride semiconductor wafer or nitride semiconductor device made by the same; and laser irradiating apparatus used for the same To remove the disparate substrate from nitride semiconductor layer grown over the disparate substrate, that is made of a material different from nitride semiconductor, by irradiating the disparate substrate with laser beam having a wavelength shorter than the band g...	10/28/2008
7439184	Method of making comb-teeth electrode pair A pair of comb-teeth electrodes are made from a material substrate including a first conduction layer, a second conduction layer and an intervening insulation layer. The paired electrodes includes first and second comb-teeth electrodes. The first comb-teeth electrod...	10/21/2008
7419906	Method for manufacturing a through conductor A method of manufacturing a through conductor that penetrates from an upper surface of a silicon substrate to its lower surface. The through conductor is manufactured in steps which provide a first conductor which extends in the direction of thickness of the silicon...	09/02/2008
7416977	Method for manufacturing display device, liquid crystal television, and EL television An object of the present invention is to provide a method for manufacturing a display device with few steps and high yield. One feature of the invention is to form a first mask pattern having low wettability over a conductive layer, form a second mask pattern having...	08/26/2008
7393768	Etching of structures with high topography The present invention relates to a method for the patterning of a stack of layers on a surface with high topography. A method of the present invention can be used for gate patterning for multiple Gate FETs (MuGFETs), for patterning of the control gate in non-volatil...	07/01/2008
7368395	Method for fabricating a nano-imprinting mold An imprinting apparatus and method of fabrication provide a mold having a pattern for imprinting. The apparatus includes a semiconductor substrate polished in a [110] direction. The semiconductor substrate has a (110) horizontal planar surface and vert...	05/06/2008
7297636	Methods for fabricating device features having small dimensions Methods for fabricating devices having small feature sizes are provided. In an exemplary embodiment, a method comprises forming a patterned first mask layer overlying a subject material layer and isotropically etching the patterned first mask layer. A second masking...	11/20/2007
7262134	Microfeature workpieces and methods for forming interconnects in microfeature workpieces Methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. In one embodiment, a method of forming an interconnect in a microfeature workpiece includes forming a hole extending through a t...	08/28/2007
7250335	Methods of fabricating integrated circuit devices including self-aligned contacts with increased alignment margin An integrated circuit device, e.g., a memory device, includes a substrate, and a plurality of rows of active regions in the substrate, the active regions arranged in a staggered pattern such that active regions of a first row are aligned with portions of an isolatio...	07/31/2007
7169711	Method of using carbon spacers for critical dimension (CD) reduction A method of using carbon spacers for critical dimension reduction can include providing a patterned photoresist layer above a substrate where the patterned photoresist layer has an aperture with a first width, depositing a carbon film over the photoresist layer and ...	01/30/2007
7132366	Method for fabricating semiconductor components using conductive layer and grooves A method for fabricating semiconductor components such as printed circuit boards, multi chip modules, chip scale packages, and test carriers is provided. The method includes providing a substrate having a blanket deposited conductive layer thereon. Using a laser mac...	11/07/2006
6613667	Forming an interconnect of a semiconductor device Forming an interconnect of a semiconductor device includes defining a recessed structure proximate to an outer surface of a substrate of a semiconductor device. A metal layer is deposited within the recessed structure. A region of the metal layer is expos...	09/02/2003
6472329	Etching aluminum over refractory metal with successive plasmas A process and apparatus for etching an exposed region of a multi-layer metal having at least two layers: a layer of aluminum or aluminum alloy, and an underlying layer of refractory metal. The etching process includes at least two steps. In a first step, ...	10/29/2002
6407443	Nanoscale patterning for the formation of extensive wires A method for forming a platen useful for forming nanoscale wires for device applications comprises: (a) providing a substrate having a major surface; (b) forming a plurality of alternating layers of two dissimilar materials on the substrate to form a stac...	06/18/2002
6380582	Autoaligned etching process for realizing word lines in memory devices integrated semiconductor substrates Self-aligned etching process for providing a plurality of mutually parallel word lines in a first conducting layer deposited over a plagiarized architecture obtained starting from a semiconductor substrate on which is provided a plurality of active elemen...	04/30/2002
6294450	Nanoscale patterning for the formation of extensive wires A method for forming a platen useful for forming nanoscale wires for device applications comprises: (a) providing a substrate having a major surface; (b) forming a plurality of alternating layers of two dissimilar materials on the substrate to form a stac...	09/25/2001
6255227	Etching process of CoSi2 layers The present invention relates to methods for controlling the etching rate of CoSi2 layers by adjusting the pH of an HF-based solution to obtain the desired etch rate. The pH of the HF-based solution may be adjusted by adding pH modifying chemic...	07/03/2001
6239037	Autoaligned etching process for realizing word lines and improving the reliability of semiconductor integrated memory devices The process proposed allows provision of a matrix topography for electronic memory devices using self-alignment etchings capable of removing those spurious electrical contacts between adjacent memory cells. The self-aligned etching process proposed for pr...	05/29/2001
6153484	Etching process of CoSi₂ layers The present invention relates to methods for controlling the etching rate of CoSi2 layers by adjusting the pH of an HF-based solution to obtain the desired etch rate. The pH of the HF-based solution may be adjusted by adding pH modifying chemic...	11/28/2000
6130165	Autoaligned etching process for realizing word lines in memory devices integrated semiconductor substrates Self-aligned etching process for providing a plurality of mutually parallel word lines in a first conducting layer deposited over a planarized architecture obtained starting from a semiconductor substrate on which is provided a plurality of active element...	10/10/2000
6103633	Method for cleaning metal precipitates in semiconductor processes A new method of cleaning metal precipitates after the etching of metal lines using a two-step process is described. Semiconductor device structures are provided in and on a semiconductor substrate. The semiconductor device structures are covered with an i...	08/15/2000
6087266	Methods and apparatus for improving microloading while etching a substrate A method for improving microloading of a substrate to be etched in a plasma processing chamber. The substrate is etched with a first etchant to form trenches having a given trench width. The plasma processing chamber has a first power supply configured to...	07/11/2000
5993686	Fluoride additive containing chemical mechanical polishing slurry and method for use of same A chemical mechanical polishing slurry comprising an oxidizing agent, a fluoride containing additive and an abrasive and a method for using the fluoride containing additive chemical mechanical polishing slurry to remove tungsten and titanium from substrat...	11/30/1999
5840630	FBI etching enhanced with 1,2 di-iodo-ethane A focused ion beam is used to etch material from a specimen while directing a vapor of 1,2 di-iodo-ethane at the surface being etched. The etch rate is accelerated for surfaces of aluminum and gold relative to the etch rate without use of 1,2 di-iodo-etha...	11/24/1998
5834125	Non-reactive anti-reflection coating An anti-reflection coating is provided that has a barrier layer and an anti-reflective layer. The barrier layer stops reactions between the anti-reflective layer and underlying layers or substrates, does not make the anti-reflective layer reflective, and ...	11/10/1998
5820926	Process for forming and using a non-reactive anti-reflection coating An anti-reflection coating is provided that has a barrier layer and an anti-reflective layer. The barrier layer stops reactions between the anti-reflective layer and underlying layers or substrates, does not make the anti-reflective layer reflective, and ...	10/13/1998
5801101	Method of forming metal wirings on a semiconductor substrate by dry etching Disclosed herein is, a method of forming a metal wiring on a semiconductor substrate dry etching a metal wiring film or a laminated structure film comprising a metal wiring film and a metal barrier film, which includes a first step of performing etching t...	09/01/1998
5767013	Method for forming interconnection in semiconductor pattern device A method for forming an interconnection pattern in a semiconductor device for reducing metallic reflection, includes the steps of forming a conductive layer on a substrate, polishing the conductive layer to form a rugged surface on the conductive layer, a...	06/16/1998
5736002	Methods and equipment for anisotropic, patterned conversion of copper into selectively removable compounds and for removal of same Methods and equipment for anisotropic, patterned conversion of copper into selectively removable compounds and for removal of the same are disclosed. In one embodiment a plasma reactor is used to anisotropically convert unmasked portions of a copper layer...	04/07/1998
5672282	Process to preserve silver metal while forming integrated circuits A process to form integrated circuits comprising silver metal circuits. Deposition techniques such as sputtering, not plating, upon substrates to form such silver metal circuits are common. However in the conventional processes to remove the resist and th...	09/30/1997
5662819	Plasma processing method with controlled ion/radical ratio Controlling ion/radical ratio and monoatomic/polyatomic radical ratio in a process plasma provides improved processing performance during inductively-coupled plasma and/or helicon wave plasma processing of substrate materials. In a plasma processing metho...	09/02/1997
5614444	Method of using additives with silica-based slurries to enhance selectivity in metal CMP A method of using additives with silica-based slurries to enhance metal selectivity in polishing metallic materials utilizing a chemical-mechanical polishing (CMP) process. Additives are used with silica-based slurries to passivate a dielectric surface, s...	03/25/1997
5607718	Polishing method and polishing apparatus This invention provides a polishing method including the steps of forming a film to be polished on a substrate having a recessed portion in its surface so as to fill at least the recessed portion, and selectively leaving the film to be polished behind in ...	03/04/1997
5598317	Laser patterned semiconductor capacitor A semiconductor capacitor used to test for contaminants in a fabrication line is created by: forming a layer of insulating material on a semiconductor substrate, forming a layer of conductive thin film on the layer of insulating material, and laser patter...	01/28/1997
5583070	Process to form rugged polycrystalline silicon surfaces A process for fabricating stacked capacitor, DRAM, devices, has been developed in which the surface area of the storage node has been significantly increased as a result of a unique set of deposition and annealing conditions. An amorphous polysilicon laye...	12/10/1996
5505322	Process for etching copper containing metallic film and forming copper containing metallic wiring A process for dry etching a copper containing film formed on a substrate is performed by using an etching gas while heating at a temperature below 200° C. The etching gas is selectable from the group consisting of a mixed gas of a N containing gas, an O ...	04/09/1996
5474949	Method of fabricating capacitor or contact for semiconductor device by forming uneven oxide film and reacting silicon with metal containing gas A method of the invention for fabricating a semiconductor device includes the steps of: forming an oxide film having a non-uniform thickness on silicon; reducing at least a portion of the oxide film using gas containing a metal element, and growing a meta...	12/12/1995
5449639	Disposable metal anti-reflection coating process used together with metal dry/wet etch A new method of metal etching using a disposable metal antireflective coating process along with metal dry/wet etching is described. An insulating layer is provided over semiconductor device structures in and on a semiconductor substrate. Openings are mad...	09/12/1995
5416048	Method to slope conductor profile prior to dielectric deposition to improve dielectric step-coverage A process for semiconductor manufacture in which the top corners of conductive features are preferentially etched compared to the etch rate of the vertical and horizontal surfaces, thereby creating a sloped (prograde) profile, i.e., facets. The material r...	05/16/1995
4868137	Method of making insulated-gate field effect transistor A method of manufacturing an insulated-gate field effect transistor is comprised of forming on a semiconductor substrate a gate electrode elecrically insulated from the substrate. A flat insulating film of silicon oxide is formed over the substrate. A pai...	09/19/1989

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Class 257/E21.305 - Physical or chemical etching of layer, e.g., to produce a patterned layer from pre-deposited extensive layer (EPO)