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| Number | Title | Issue Date |
| 7439185 | Method for fabricating semiconductor device and semiconductor device A method of fabricating a semiconductor device having an air-gapped multilayer interconnect wiring structure is disclosed. After having formed a first thin film on or above a substrate, define a first opening in the first thin film. Then, deposit a conductive materi... | 10/21/2008 |
| 7435674 | Dielectric interconnect structures and methods for forming the same Dielectric interconnect structures and methods for forming the same are provided. Specifically, the present invention provides a dielectric interconnect structure having a noble metal layer (e.g., Ru, Ir, Rh, Pt, RuTa, and alloys of Ru, Ir, Rh, Pt, and RuTa) that is... | 10/14/2008 |
| 7432200 | Filling narrow and high aspect ratio openings using electroless deposition Methods of fabricating an interconnect utilizing an electroless deposition technique, which fundamentally consists of providing a dielectric material layer having an opening extending into the dielectric material from a first surface thereof, and electrolessly depos... | 10/07/2008 |
| 7427561 | Method for manufacturing semiconductor device A semiconductor device manufacturing method wherein a metal suicide layer is formed via an in-situ process. The method includes forming a gate electrode on a semiconductor substrate; forming an insulation side wall at either lateral surface of the gate electrode; fo... | 09/23/2008 |
| 7422982 | Method and apparatus for electroprocessing a substrate with edge profile control A method and apparatus for electroprocessing a substrate is provided. In one embodiment, a method for electroprocessing a substrate includes the steps of biasing a first electrode to establish a first electroprocessing zone between the electrode and the substrate, a... | 09/09/2008 |
| 7419906 | Method for manufacturing a through conductor A method of manufacturing a through conductor that penetrates from an upper surface of a silicon substrate to its lower surface. The through conductor is manufactured in steps which provide a first conductor which extends in the direction of thickness of the silicon... | 09/02/2008 |
| 7416987 | Semiconductor device and method of fabricating the same According to the present invention, there is a provided a semiconductor device fabrication method having, forming a mask material in a surface portion of a semiconductor substrate, and forming a step having a projection by using the mask material; forming a dielectr... | 08/26/2008 |
| 7416942 | Method for manufacturing semiconductor device A method for manufacturing a semiconductor device is provided. The method includes successively forming a first silicon film and a mask film above a semiconductor substrate through a gate insulating film, forming a plurality of trenches in the first silicon film and... | 08/26/2008 |
| 7413989 | Method of manufacturing semiconductor device A semiconductor wafer including an underlying layer including an insulating film having at least one recess therein and a metallic material layer formed over a top surface of the underlying layer and filling the recess, on a semiconductor substrate, is subjected to ... | 08/19/2008 |
| 7410854 | Method of making FUSI gate and resulting structure Generally disclosed is a method of a device comprising forming a polysilicon stack including a first and a second polysilicon layer with an intervening etch stop layer, wherein the first polysilicon layer height is at least one third a height of the polysilicon stac... | 08/12/2008 |
| 7408215 | Dynamic random access memory A DRAM structure on a silicon substrate has an active area, gate conductors, deep trench capacitors, and vertical transistors. The deep trench capacitors are formed at intersections of the active area and the gate conductors, and each deep trench capacitor is couple... | 08/05/2008 |
| 7397074 | RF field heated diodes for providing thermally assisted switching to magnetic memory elements An exemplary array of thermally-assisted magnetic memory structures includes a plurality of magnetic memory elements, each magnetic memory element being near a diode. A diode near a selected magnetic memory element can be heated by absorbing energy from a radio freq... | 07/08/2008 |
| 7397075 | Method and apparatus providing CMOS imager device pixel with transistor having lower threshold voltage than other imager device transistors A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of about 0.3 V to less than about 0.7 V is disclosed. The transistor is provided with high dosage source and drain regions around the gate electrode and with the halo implanted region... | 07/08/2008 |
| 7390744 | Method and composition for polishing a substrate Polishing compositions and methods for removing conductive materials and barrier materials from a substrate surface are provided. Polishing compositions are provided for removing at least a barrier material from a substrate surface by a chemical mechanical polishing... | 06/24/2008 |
| 7384841 | DRAM device and method of manufacturing the same In a DRAM device and a method of manufacturing the same, a multiple tunnel junction (MTJ) structure is provided, which includes conductive patterns and nonconductive patterns alternately stacked on each other. The nonconductive patterns have a band gap larger than a... | 06/10/2008 |
| 7384834 | Semiconductor device and a method of manufacturing the same A semiconductor device and a method of manufacturing such a semiconductor device having a field effect transistor with improved current driving performance (e.g., an increase of drain current) of the field effect transistor comprising the steps of ion implanting an ... | 06/10/2008 |
| 7384833 | Stress liner for integrated circuits In one embodiment, a self-aligned contact (SAC) trench structure is formed through a dielectric layer to expose an active region of a MOS transistor. The SAC trench structure not only exposes the active region for electrical connection but also removes portions of a... | 06/10/2008 |
| 7368383 | Hillock reduction in copper films A method for treating a copper surface of a semiconductor device provides exposing the copper surface to a citric acid solution after the surface is formed using CMP (chemical mechanical polishing) or other methods. The citric acid treatment may take place during a ... | 05/06/2008 |
| 7365009 | Structure of metal interconnect and fabrication method thereof A process and structure for a metal interconnect includes providing a substrate with a first electric conductor, forming a first dielectric layer and a first patterned hard mask, using the first patterned hard mask to form a first opening and a second electric condu... | 04/29/2008 |
| 7361603 | Passivative chemical mechanical polishing composition for copper film planarization A CMP composition containing 5-aminotetrazole, e.g., in combination with oxidizing agent, chelating agent, abrasive and solvent and a method of use. Such CMP composition may be diluted during the CMP polish to minimize the occurrence of dishing or other adverse plan... | 04/22/2008 |
| 7361539 | Dual stress liner A semiconductor device structure is provided which includes a first field effect transistor (“FET”) having a first channel region, a first source region, a first drain region and a first gate conductor overlying the first channel region. A second FET is included... | 04/22/2008 |
| 7348231 | Methods of fabricating semiconductor devices having insulating layers with differing compressive stresses Methods of fabricating semiconductor devices are provided. An NMOS transistor and a PMOS transistor are provided on a substrate. The NMOS transistor is positioned on an NMOS region of the substrate and the PMOS transistor is positioned on a PMOS region of the substr... | 03/25/2008 |
| 7344987 | Method for CMP with variable down-force adjustment The present invention relates to a method for performing chemical mechanical polishing. A high down-force step is performed. A low down-force step is performed. At least one of the down-force steps is modified, based on if one of the down-force steps exceeds an acce... | 03/18/2008 |
| 7344954 | Method of manufacturing a capacitor deep trench and of etching a deep trench opening A substrate is provided having an oxide layer, a first nitride-silicon, a STI, and a second nitride-silicon. A pattern poly-silicon layer on the second nitride-silicon layer is etched to form a deep trench opening. Etching the pattern poly-silicon layer also deepens... | 03/18/2008 |
| 7341908 | Semiconductor device and method of manufacturing the same Provided are a semiconductor device including a reliable interconnect and a method of manufacturing the same. The semiconductor device includes a substrate, an inter-metal dielectric (IMD) pattern having an opening, an amorphous metallic nitride layer formed on the ... | 03/11/2008 |
| 7341948 | Method of making a semiconductor structure with a plating enhancement layer Disclosed is a method of making a semiconductor structure, wherein the method includes forming an interlayer dielectric (ILD) layer on a semiconductor layer, forming a conductive plating enhancement layer (PEL) on the ILD, patterning the ILD and PEL, depositing a se... | 03/11/2008 |
| 7338882 | Method of fabricating nano SOI wafer and nano SOI wafer fabricated by the same A method of fabricating a nano silicon on insulator (SOI) wafer having an excellent thickness evenness without performing a chemical mechanical polishing (CMP) and a wafer fabricated by the same are provided. The provided method includes preparing a bond wafer and a... | 03/04/2008 |
| 7339226 | Dual-level stacked flash memory cell with a MOSFET storage transistor The present invention is a dual-level flash memory cell design that stores 3 or more bits of information per transistor. The dual-level memory cell stores two lower bits in a first level and stores an upper bit in a second level. The lower bits are programmed, erase... | 03/04/2008 |
| 7338905 | Semiconductor device manufacture method An electric conductive film is formed on the insulating surface of a substrate, the substrate having a trench formed on the insulating surface, and the conductive film being filled in the trench. Chemical mechanical polishing is executed to expose the insulating sur... | 03/04/2008 |
| 7332425 | Simultaneous deposition and etch process for barrier layer formation in microelectronic device interconnects The present invention provides a method of forming a interconnect barrier layer 100. In the method, physical vapor deposition of barrier material 200 is performed within an opening 140 located in a dielectric layer 135 of a substrate 1... | 02/19/2008 |
| 7329606 | Semiconductor device having nanowire contact structures and method for its fabrication A semiconductor device having small electrical contacts to impurity doped regions and a method for fabrication of such a device are provided. In accordance with one embodiment of the invention the semiconductor device comprises a semiconductor substrate having a dop... | 02/12/2008 |
| 7327009 | Selective nitride liner formation for shallow trench isolation A method for forming a divot free nitride lined shallow trench isolation (STI) feature including providing a substrate including an STI trench extending through an uppermost hardmask layer into a thickness of the substrate exposing the substrate portions; selectivel... | 02/05/2008 |
| 7314823 | Chemical mechanical polishing composition and process A composition for chemical mechanical polishing includes a slurry. A sufficient amount of a selectively oxidizing and reducing compound is provided in the composition to produce a differential removal of a metal and a dielectric material. A pH adjusting compound adj... | 01/01/2008 |
| 7312151 | System for ultraviolet atmospheric seed layer remediation The present invention provides a system for removing organic contaminants (216) from a copper seed layer that has been deposited on a semiconductor substrate (206). The present invention provides a housing (204) to enclose the semiconductor subs... | 12/25/2007 |
| 7306955 | Method of performing a double-sided process A method of performing a double-sided process is provided. First, a wafer having a structural pattern disposed on the front surface is provided. Following that, a plurality of front scribe lines are defined on the structural pattern, and a filling layer is filled in... | 12/11/2007 |
| 7307021 | Method for planarizing a thin film A layer of required material, such as polysilicon, is planarized by first forming a sacrificial layer of material, such as an oxide, on the layer of required material. The combined layers of required and sacrificial materials are then planarized using chemical-mecha... | 12/11/2007 |
| 7303971 | MSM binary switch memory device A metal/semiconductor/metal (MSM) binary switch memory device and fabrication process are provided. The device includes a memory resistor bottom electrode, a memory resistor material over the memory resistor bottom electrode, and a memory resistor top electrode over... | 12/04/2007 |
| 7297558 | Method of manufacturing semiconductor device A W plug (24) is formed and a W oxidation preventing barrier metal film (25) is formed thereon. After that, an SiON film (27) thinner than the W oxidation preventing barrier metal film (25) is formed and Ar sputter etching is performed on... | 11/20/2007 |
| 7288458 | SOI active layer with different surface orientation A wafer having an SOI configuration and active regions having different surface orientations for different channel type transistors. In one example, semiconductor structures having a first surface orientation are formed on a donor wafer. Semiconductor structures hav... | 10/30/2007 |
| 7285494 | Multiple stage electroless deposition of a metal layer A multiple stage method of electrolessly depositing a metal layer is presented. This method may have the two main stages of first forming a thin metal layer on a metal surface using an electroless plating solution containing activating agents that are highly reactiv... | 10/23/2007 |
