Bizarre Patents
A new toilet tank assembly aquarium for housing aquatic creatures.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7399649 | Semiconductor light-emitting device and fabrication method thereof An underlying layer ALY of GaN is formed on a sapphire substrate SSB; a transfer layer TLY of GaN with a bump and dip shaped surface is formed on the underlying layer ALY; a light absorption layer BLY is formed on the bump and dip shaped surface of the transfer laye... | 07/15/2008 |
| 7375023 | Method and apparatus for chemical mechanical polishing of semiconductor substrates Methods and apparatus for processing substrates to improve polishing uniformity, improve planarization, remove residual material and minimize defect formation are provided. In one aspect, a method is provided for processing a substrate having a conductive material a... | 05/20/2008 |
| 7307021 | Method for planarizing a thin film A layer of required material, such as polysilicon, is planarized by first forming a sacrificial layer of material, such as an oxide, on the layer of required material. The combined layers of required and sacrificial materials are then planarized using chemical-mecha... | 12/11/2007 |
| 7247555 | Method to control dual damascene trench etch profile and trench depth uniformity A method of forming trench openings in a dual damascene trench and via etch process by using a two component hard mask layer, termed a bi-layer, over different intermetal dielectrics, IMD, to solve dual damascene patterning problems, such as, fencing and sub-trench ... | 07/24/2007 |
| 7229926 | Method of manufacturing nitride substrate for semiconductors, and nitride semiconductor substrate In an independent GaN film manufactured by creating a GaN layer on a base heterosubstrate using vapor-phase deposition and then removing the base substrate, owing to layer-base discrepancy in thermal expansion coefficient and lattice constant, warp will be a large Â... | 06/12/2007 |
| 7208831 | Semiconductor device having multilayer wiring structure and method, wherein connecting portion and wiring layer are formed of same layer A method for manufacturing a semiconductor device includes a step of forming a first groove in a first insulating film, forming a conductive film in the first groove, a step of selectively forming a second insulating film on the conductive film and the first insulat... | 04/24/2007 |
| 6696358 | Viscous protective overlayers for planarization of integrated circuits The present invention relates to the planarization of surfaces as typically encountered in the fabrication of integrated circuits, particularly copper conductors and Ta/TaN barrier layers encountered in damascene and dual damascene interconnects. The pres... | 02/24/2004 |
| 6695962 | Anode designs for planar metal deposits with enhanced electrolyte solution blending and process of supplying electrolyte solution using such designs An anode assembly by which a solution can be supplied to a surface of a semiconductor substrate includes a housing defining an internal housing volume into which the solution can flow. A closure is provided for the internal housing volume, and the solutio... | 02/24/2004 |
| 6670226 | Planarizing method for fabricating gate electrodes Within a method for fabricating a semiconductor integrated circuit microelectronic fabrication, there is employed a planarizing method for forming, in a self aligned fashion, a patterned second gate electrode material layer laterally adjacent but not over... | 12/30/2003 |
| 6645869 | Etching back process to improve topographic planarization of a polysilicon layer An etching back process to improve topographic planarization of a polysilicon layer. First, a polysilicon layer is formed to fill a contact hole between two adjacent insulating structures and cover the entire surface of a semiconductor substrate to a pred... | 11/11/2003 |
| 6613667 | Forming an interconnect of a semiconductor device Forming an interconnect of a semiconductor device includes defining a recessed structure proximate to an outer surface of a substrate of a semiconductor device. A metal layer is deposited within the recessed structure. A region of the metal layer is expos... | 09/02/2003 |
| 6613240 | Method and apparatus for smoothing thin conductive films by gas cluster ion beam A method and apparatus is disclosed that provided for the successful and precise smoothing of conductive films on insulating films or substrates. The smoothing technique provides a smooth surface that is substantially free of scratches. By supplying a sou... | 09/02/2003 |
| 6602787 | Method for fabricating semiconductor devices The present invention is to provide a method for fabricating semiconductor devices capable of eliminating a height difference on a base member caused by a residual plating seed layer remained in a portion where an electrode comes into contact and is thus ... | 08/05/2003 |
| 6600229 | Planarizers for spin etch planarization of electronic components An electronic component contemplated comprises a) a substrate layer, b) a dielectric layer coupled to the substrate layer, c) a barrier layer coupled to the dielectric layer, d) a conductive layer coupled to the barrier layer, and e) a protective layer co... | 07/29/2003 |
| 6537919 | Process to remove micro-scratches Although CMP has been widely used with generally good results, one remaining problem is the occasional appearance of micro-scratches on the finished surface. Such micro-scratches may also be generated as a byproduct of processes other than CMP. The presen... | 03/25/2003 |
| 6489201 | Method for manufacturing a semiconductor device Disclosed is a method for manufacturing a semiconductor device. A polysilicon layer is deposited on an oxide layer having a contact hole or an opening. The polysilicon layer is etched-back such that the polysilicon layer remains only in the contact hole o... | 12/03/2002 |
| 6455370 | Method of patterning noble metals for semiconductor devices by electropolishing An electropolishing process for high resolution patterning of noble metals, such as platinum, for forming various semiconductor devices, such as capacitors or wiring patterns is disclosed.... | 09/24/2002 |
| 6447668 | Methods and apparatus for end-point detection An apparatus for detecting the end-point of an electropolishing process of a metal layer formed on a wafer includes an end-point detector. The end-point detector is disposed adjacent the nozzle used to electropolish the wafer. In one embodiment, the end-p... | 09/10/2002 |
| 6440295 | Method for electropolishing metal on semiconductor devices An electropolishing apparatus for polishing a metal layer formed on a wafer (31) includes an electrolyte (34), a polishing receptacle (100), a wafer chuck (29), a fluid inlet (5, 7, 9), and at least one cathode (1, 2, 3). The wafer chuck (29) holds and po... | 08/27/2002 |
| 6432825 | Semiconductor device production method To provide a semiconductor device production method capable of solving the problem of the latent period of time in which polishing is hardly performed immediately after a polishing start. In order to reduce the latent period of time caused immediately aft... | 08/13/2002 |
| 6403475 | Fabrication method for semiconductor integrated device Annealing technology is capable of heating a wafer on which a copper film is formed at a desired temperature within a short period of time. A light-shielding plate 106 of SiC (silicon carbide) exhibiting a flat emissivity irrespective of the wavelengths a... | 06/11/2002 |
| 6395152 | Methods and apparatus for electropolishing metal interconnections on semiconductor devices An electropolishing apparatus for polishing a metal layer formed on a wafer (31) includes an electrolyte (34), a polishing receptacle (100), a wafer chuck (29), a fluid inlet (5, 7, 9), and at least one cathode (1, 2, 3). The wafer chuck (29) holds and po... | 05/28/2002 |
| 6350689 | Method to remove copper contamination by using downstream oxygen and chelating agent plasma A method of removing copper contamination from a semiconductor wafer, comprising the following steps. A semiconductor wafer having copper contamination thereon is provided. An oxidizing radical containing downstream plasma is provided from a first source ... | 02/26/2002 |
| 6329289 | Method and apparatus for forming copper wiring A copper layer is formed in wiring grooves formed in a semiconductor substrate and also on the semiconductor substrate. The semiconductor substrate is brought into contact with a culture solution containing bacteria whose size is larger than the width of ... | 12/11/2001 |
| 6325676 | Gas etchant composition and method for simultaneously etching silicon oxide and polysilicon, and method for manufacturing semiconductor device using the same A gas etchant composition and a method for simultaneously etching-back silicon oxide and polysilicon at substantially similar etching rates are used for manufacturing semiconductor devices. The gas etchant composition to be utilized for dry-etching includ... | 12/04/2001 |
| 6299741 | Advanced electrolytic polish (AEP) assisted metal wafer planarization method and apparatus In advanced electrolytic polish (AEP) method, a metal wafer (10) acts as an anodic electrodes and another metal plate (65) is used as a cathodic electrode. A voltage differential is applied to the anode and cathode under a predetermined anodic dissolution... | 10/09/2001 |
| 6297558 | Slurry filling a recess formed during semiconductor fabrication The present invention advantageously provides a method for filling a recess with a slurry that exhibits electrical properties similar to those of the structure which has the recess. The topological surface that includes the recess may be placed adjacent t... | 10/02/2001 |
| 6274245 | Foil for use in filing substrate recesses To fill a hole or trench structure in an article, such as a semiconductor wafer, a layer is formed on the article. The layer extends over the structure so as to seal the mouth thereof. The layer may be deposited by sputtering, etc, or the layer may be dep... | 08/14/2001 |
| 6242356 | Etchback method for forming microelectronic layer with enhanced surface smoothness A method for forming a microelectronic layer within a microelectronic fabrication first employs a substrate. There is then formed over the substrate a target microelectronic layer. There is then formed upon the target microelectronic layer a sacrificial s... | 06/05/2001 |
| 6232233 | Methods for performing planarization and recess etches and apparatus therefor A method, in an RF-based plasma processing chamber 600, for performing a planarization etch and a recess etch of a first layer on a semiconductor wafer 614. The method includes placing the semiconductor wafer, including a trench formed therein, into the p... | 05/15/2001 |
| 6207483 | Method for smoothing polysilicon gate structures in CMOS devices There is provided a method for smoothing the surface of undoped polysilicon regions of a CMOS structure, primarily gate regions. A direct HPD-CVD argon sputter is used improve the surface roughness by a factor of more than 50%. The argon plasma sputter ma... | 03/27/2001 |
| 6205658 | Method for formation of metal wiring A metal wiring forming process in which an insulating film is formed on the principal surface of a substrate. Grooves or via holes are formed in the insulating layer and then a barrier film and a metal film in this order are formed on the substrate. There... | 03/27/2001 |
| 6194296 | Method for making planarized polycide Planarized polycide structures and methods for making the same. One embodiment includes a semiconductor structure having an irregular upper surface caused, for example, by the presence of field oxide surrounding an active region of an FET. A layer of poly... | 02/27/2001 |
| 6143155 | Method for simultaneous non-contact electrochemical plating and planarizing of semiconductor wafers using a bipiolar electrode assembly Simultaneous non-contact plating and planarizing of copper interconnections in semiconductor wafer manufacturing is performed by providing relative motion between a bipolar electrode and a metallized surface of a semiconductor wafer without necessary phys... | 11/07/2000 |
| 6121152 | Method and apparatus for planarization of metallized semiconductor wafers using a bipolar electrode assembly Planarization of metal interconnections in semiconductor wafer manufacturing is performed by providing relative motion between a bipolar electrode assembly scanned and a single metallized surface of a semiconductor wafer without necessary physical contact... | 09/19/2000 |
| 6117755 | Method for planarizing the interface of polysilicon and silicide in a polycide structure A method for planarizing the interface of polysilicon and silicide in a polycide structure is presented in this invention. It is by regulating the process temperature when depositing polysilicon to meanwhile improve its planarization. At first, a doped po... | 09/12/2000 |
| 6106683 | Grazing angle plasma polisher (GAPP) A device and method for polishing the surface of a substrate uses a vessel for holding a plasma in a magnetic field. Further, the magnetic field is selectively oriented in the vessel relative to the substrate surface. An ion accelerator is then activated ... | 08/22/2000 |
| 6087191 | Method for repairing surface defects A method for repairing defects in a surface layer of a substrate. The method comprises the redeposition, in a solvent environment, of a fill material into the defects of the surface layer. The fill material is provided by the surface layer itself or from ... | 07/11/2000 |
| 6071816 | Method of chemical mechanical planarization using a water rinse to prevent particle contamination A method of chemical mechanical planarization of a semiconductor device provides a semiconductor device having a device front surface and a device back surface with the device front surface being a top surface of a second metal layer. A first planarizing ... | 06/06/2000 |
| 6069085 | Slurry filling a recess formed during semiconductor fabrication The present invention advantageously provides a method for filling a recess with a slurry that exhibits electrical properties similar to those of the structure which has the recess. The topological surface that includes the recess may be placed adjacent t... | 05/30/2000 |
