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| Number | Title | Issue Date |
| 7166543 | Methods for forming an enriched metal oxide surface for use in a semiconductor device Methods of forming a metal oxide surface that is enriched with metal oxide in its higher oxidation state for use in a semiconductor device are provided. A metal oxide surface that is enriched with metal oxide in its higher oxidation state for use in a semiconductor ... | 01/23/2007 |
| 6692588 | Method and apparatus for simultaneously cleaning and annealing a workpiece The present invention is directed to a method and apparatus for simultaneously cleaning and annealing a plated semiconductor workpiece. A chamber for simultaneously cleaning and annealing a semiconductor workpiece is provided herein. The method according ... | 02/17/2004 |
| 6690044 | Approach to avoid buckling BPSG by using an intermediate barrier layer A multilayer heterostructure is provided a planarization layer superjacent a semiconductor substrate. The planarization layer comprises tungsten, titanium, tantalum, copper, aluminum, single crystal silicon, polycrystalline silicon, amorphous silicon, bor... | 02/10/2004 |
| 6682659 | Method for forming corrosion inhibited conductor layer A method for passivating a target layer. There is first provided a substrate. There is then formed over the substrate a target layer, where the target layer is susceptible to corrosion incident to contact with a corrosive material employed for further pro... | 01/27/2004 |
| 6648987 | Method for producing nanostructures in thin films The invention relates to a method for producing a layer with a sub-micrometre structure on a substrate. First, a layer is formed on the substrate. Agents for creating elastic strains are then formed in at least one predetermined position on the layer and ... | 11/18/2003 |
| 6645803 | Method for modifying the doping level of a silicon layer A method for modifying the doping level of a doped silicon layer including the steps of coating the silicon layer with a silicide layer made of a refractory metal, and heating the interface region between the silicon and the silicide to a predetermined te... | 11/11/2003 |
| 6620700 | Silicided undoped polysilicon for capacitor bottom plate A capacitor (110) having a bottom plate (104) that includes undoped polysilicon (106) which has been silicided (108). An advantage of the invention is providing a capacitor (110) having reduced parasitic capacitance to the substrate (100) and reduced shee... | 09/16/2003 |
| 6617624 | Metal gate electrode stack with a passivating metal nitride layer A low resistance gate stack for an integrated circuit transistor is provided including a metal layer having a first width and a metal nitride over surfaces of the metal layer being less than about 20 Å. The gate stack further includes a doped polysilicon... | 09/09/2003 |
| 6602653 | Conductive material patterning methods A patterning method includes providing a first material (e.g., copper) and transforming at a least a surface region of the first material to a second material (e.g., copper oxide). One or more portions of the second material (e.g., copper oxide) are conve... | 08/05/2003 |
| 6548387 | Method for reducing hole defects in the polysilicon layer A method for reducing hole defects in the polysilicon layer. The method at least includes the following steps. First of all, a semiconductor substrate is provided, a polysilicon layer is formed over the semiconductor substrate. Then, no hole defects botto... | 04/15/2003 |
| 6525404 | Moisture corrosion inhibitor layer for Al-alloy metallization layers, particularly for electronic devices and corresponding manufacturing method A method of producing a protective inhibitor layer of moisture-generated corrosion for aluminum (Al) alloy metallization layers, particularly in semiconductor electronic devices, includes chemically treating the metallization layer in at least two steps u... | 02/25/2003 |
| 6481616 | Bump bonding device and bump bonding method To eliminate breakage of electronic parts or defective bonding, and enhance reliability of electronic parts, in regulation of electronic parts in bump bonding device. A bump bonding device comprising a stage 1 for mounting and heating an electronic part, ... | 11/19/2002 |
| 6479383 | Method for selective removal of unreacted metal after silicidation A method to remove a metal from over a substrate in the fabrication of an integrated circuit device. The invention comprises providing a metal layer over a substrate. The metal layer is exposed to a reactant gas to form at least a solid metal containing p... | 11/12/2002 |
| 6423635 | Method of filling a recess The invention relates to a process for filling a multiplicity of recesses (3) formed in an exposed surface of a workpiece (1), wherein the mouths of the recesses (3) are closed by the deposition of a layer (10) and the layer is subjected to elevated tempe... | 07/23/2002 |
| 6413866 | Method of forming a solute-enriched layer in a substrate surface and article formed thereby A method of enriching the surface of a substrate with a solute material that was originally dissolved in the substrate material, to yield a uniform dispersion of the solute material at the substrate surface. The method generally entails the use of a solve... | 07/02/2002 |
| 6398943 | Process for producing a porous layer by an electrochemical etching process A porous layer produced from silicon, germanium or aluminum by applying a wedge-shaped mask to the surface of the layer and by controlled elecrochemical etching along the mask.... | 06/04/2002 |
| 6383905 | Formation of micro rough poly surface for low sheet resistance salicided sub-quarter micron poly lines This invention relates to a method for manufacturing a semiconductor device having polysilicon lines with micro-roughness on the surface. The micro-rough surface of the polysilicon lines help produce smaller grain size silicide graiicide film during the f... | 05/07/2002 |
| 6380609 | Silicided undoped polysilicon for capacitor bottom plate A capacitor (110) having a bottom plate (104) that comprises undoped polysilicon (106) which has been silicided (108). An advantage of the invention is providing a capacitor (110) having reduced parasitic capacitance to the substrate (100) and reduced she... | 04/30/2002 |
| 6380094 | Method for preventing redeposition of etching products onto substrate surfaces during a tungsten re-etching process in the production of LSI circuits A method for back-etching of tungsten-coated substrate surfaces in the production of large-scale integrated circuits includes pressing a substrate against a cooled specimen holder during back-etching with a retaining ring being disposed on an edge of the ... | 04/30/2002 |
| 6372574 | Method of forming a capacitor container electrode and method of patterning a metal layer by selectively silicizing the electrode or metal layer and removing the silicized portion A method of patterning a metal layer includes masking a first portion of a metal layer while leaving a second portion of the metal layer unmasked over a substrate. With the masking in place, the second portion is reacted with silicon to form a metal silic... | 04/16/2002 |
| 6326284 | Semiconductor device and production thereof A semiconductor device produced by forming an oxide film on a substrate, heat treating the oxide film at a temperature of 800° C. or higher in an inert atmosphere, followed by conventional steps for formation of a transistor, is improved in electrical re... | 12/04/2001 |
| 6300243 | Refractory metal roughness reduction using high temperature anneal in hydrides or organo-silane ambients An embodiment of the present invention teaches a method used in a semiconductor fabrication process to form a memory cell in a semiconductor device comprising the steps of: subjecting a layered structure comprising a silicon gate insulating layer, a condu... | 10/09/2001 |
| 6287970 | Method of making a semiconductor with copper passivating film A method of making a semiconductor device includes the steps of forming an oxide layer adjacent a semiconductor substrate, etching trenches within the oxide layer, depositing a copper layer to at least fill the etched trenches, and forming a copper arsena... | 09/11/2001 |
| 6277745 | Passivation method of post copper dry etching The present invention relates to a new structure and method for the passivation of copper electrical interconnects for the semiconductor industry. More particularly, the invention details a convenient method for completing the passivation of copper lines ... | 08/21/2001 |
| 6265297 | Ammonia passivation of metal gate electrodes to inhibit oxidation of metal A method and apparatus is provided for wet oxidation while passivating metal elements by adsorption of a passivating species. A transistor gate stack includes a metallic layer that exhibits catalytic behavior in the presence of the passivating species. In... | 07/24/2001 |
| 6242338 | Method of passivating a metal line prior to deposition of a fluorinated silica glass layer A process of forming a thin, protective insulator layer, on the sides of metal interconnect structures, prior to the deposition of a halogen containing, low k dielectric layer, has been developed. The process features the growth of a thin metal nitride, o... | 06/05/2001 |
| 6221730 | Fabrication method of semiconductor device with HSG configuration A fabrication method of a semiconductor device is provided, which makes it possible to introduce suitably a dopant into surface grains of a semiconductor layer at a comparatively low temperature. In the first step, a first semiconductor layer is formed ov... | 04/24/2001 |
| 6218733 | Semiconductor device having a titanium-aluminum compound The present invention includes a process for forming an intermetallic layer and a device formed by the process. The process includes a reaction step where a metal-containing layer reacts with a metal-containing gas, wherein the metals of the layer and gas... | 04/17/2001 |
| 6171981 | Electrode passivation layer of semiconductor device and method for forming the same An electrode passivation layer of a semiconductor device and a method for forming the same having improved corrosion-resistance and oxidation-resistance are disclosed, the electrode passivation film including a semiconductor substrate; a conductive layer ... | 01/09/2001 |
| 6136678 | Method of processing a conductive layer and forming a semiconductor device A method for processing a conductive layer, such as a doped polysilicon layer (14) of a gate stack, provides a degas step after precleaning to reduce particle count and defectivity. The conductive layer is provided on a substrate (10), e.g., a silicon waf... | 10/24/2000 |
| 6107156 | Silicide layer forming method and semiconductor integrated circuit A surface of a conductive member such as a gate electrode provided with a silicon layer is roughened. The roughened silicon layer is silicified so that its width is substantially increased, whereby phase transition of the silicide layer is simplified. Thu... | 08/22/2000 |
| 6096645 | Method of making IC devices having stable CVD titanium nitride films A method of forming a CVD nitride (e.g., titanium nitride) film on a substrate. The as-deposited nitride film is treated by a plasma of a high power density (preferably between approximately 200 W and 300 W) for a prolonged duration of time (preferably be... | 08/01/2000 |
| 6083829 | Use of a low resistivity Cu3 Ge interlayer as an adhesion promoter between copper and tin layers A method for fabricating a copper interconnect structure, using a low resistivity Cu3 Ge intermetallic layer, as an adhesive layer, has been developed. Following an in situ, CVD of a titanium nitride barrier layer, a germanium layer, and a copp... | 07/04/2000 |
| 6071808 | Method of passivating copper interconnects in a semiconductor A method of passivating copper interconnects is disclosed. A freshly electrodeposited copper interconnect such as formed as via/trench structures in semiconductor manufacturing is chemically converted to passivating surface of copper tungstate or copper c... | 06/06/2000 |
| 6057203 | Integrated circuit capacitor A capacitor may be formed by implanting after forming a dielectric and a conductive layer over a semiconductor structure. This diminishes the implant damage to the region underneath the conductive layer. Implanted impurities may be driven under the conduc... | 05/02/2000 |
| 6049092 | Semiconductor device and method for manufacturing the same A TFT formed on an insulating substrate source, drain and channel regions, a gate insulating film formed on at least the channel region and a gate electrode formed on the gate insulating film. Between the channel region and the drain region, a region havi... | 04/11/2000 |
| 6046106 | High density plasma oxide gap filled patterned metal layers with improved electromigration resistance Borderless submicron vias are formed between patterned metal layers gap filled with a high density plasma oxide. Heat treatment is conducted after chemical vapor deposition of the high density plasma oxide to substantially increase the grain size of the p... | 04/04/2000 |
| 6040629 | Semiconductor integrated circuit having silicided elements of short length A surface of a conductive member such as a gate electrode provided with a silicon layer is roughened. The roughened silicon layer is silicified so that its width is substantially increased, whereby phase transition of the silicide layer is simplified. Thu... | 03/21/2000 |
| 6033940 | Anodization control for forming offset between semiconductor circuit elements A circuit substrate includes a plurality of semiconductor devices including electrodes, a wiring having a plurality of branched portions and mainly formed of a metal material, a terminal for applying a voltage to the wiring to anodize the branched portion... | 03/07/2000 |
| 6028002 | Refractory metal roughness reduction using high temperature anneal in hydrides or organo-silane ambients An embodiment of the present invention teaches a method used in a semiconductor fabrication process to form a memory cell in a semiconductor device comprising the steps of: subjecting a layered structure comprising a silicon gate insulating layer, a condu... | 02/22/2000 |
