Class 257/E21.296 - Of metal-silicide layer (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.295. This
No. of patents: 108
Last issue date: 04/08/2008

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Number	Title	Issue Date
7355255	Nickel silicide including indium and a method of manufacture therefor The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a substrate (110), as well as a nicke...	04/08/2008
7344985	Nickel alloy silicide including indium and a method of manufacture therefor The invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a gate structure located over a substrate, the gate ...	03/18/2008
7338815	Semiconductor device manufacturing method A semiconductor device manufacturing method, includes a step of forming refractory metal silicide layers 13a to 13c in a partial area of a semiconductor substrate 10, a step of forming an interlayer insulating film 21 on the...	03/04/2008
7256123	Method of forming an interface for a semiconductor device In a semiconductor device using a polysilicon contact, such as a poly plug between a transistor and a capacitor in a container cell, an interface is provided where the poly plug would otherwise contact the bottom plate of the capacitor. The interface bars silicon fr...	08/14/2007
7208409	Integrated circuit metal silicide method Fluorine containing regions (70) are formed in the source and drain regions (60) of the MOS transistor. A metal layer (90) is formed over the fluorine containing regions (70) and the source and drain regions (60). The metal layer i...	04/24/2007
7179702	Semiconductor device including metal insulator semiconductor field effect transistor and method of manufacturing the same A semiconductor device comprises a semiconductor substrate, an N-channel MISFET and a P-channel MISFET provided on the semiconductor substrate, each of the N- and P-channel MISFETs being isolated by an isolation region and having a gate insulating film, a first gate...	02/20/2007
7105429	Method of inhibiting metal silicide encroachment in a transistor A method inhibits metal silicide encroachment in channel regions in a transistor that uses metal silicide as an electrical contact to its terminals. A metal layer is deposited overlying the transistor. A first anneal that is a low temperature anneal forms metal sili...	09/12/2006
6699786	Method for forming a semiconductor device that uses a low resistance tungsten silicide layer with a strong adherence to an underlayer Tungsten silicide WSix is grown through reduction of WF6 with SiCl2 H2, and the flow rate between WF6 and SiCl2 H2 is controlled in such a manner that the composition ratio x ranges ...	03/02/2004
6689693	Methods for utilization of disappearing silicon hard mask for fabrication of semiconductor structures A method of forming structures in semiconductor devices through a buffer or insulator layer comprises the use of a silicon hard mask between a patterned resist layer for etching the structures and an underlying barrier layer. The silicon hard mask acts as...	02/10/2004
6686619	Dynamic random access memory with improved contact arrangements A semiconductor integrated circuit device and a manufacturing method therefor provide advantages that undulations are prevented from being produced in polycrystal silicon plugs in bit line contact holes and that the undesired phenomenon of transversally e...	02/03/2004
6667552	Low dielectric metal silicide lined interconnection system Multi-level semiconductor devices are formed with reduced parasitic capacitance without sacrificing structural integrity or electromigration performance by removing the inter-layer dielectrics and depositing a metal silicide to line the interconnection sy...	12/23/2003
6661057	Tri-level segmented control transistor and fabrication method A transistor is formed in an active area having a segmented gate structure. The segmented gate structure advantageously provides for dynamic control of a channel region formed within the transistor. Lightly doped source and drain (LDD) regions are formed ...	12/09/2003
6661048	Semiconductor memory device having self-aligned wiring conductor According to the present invention, an overlay margin is secured for matching a wiring electrode 11 with a storage electrode 15 of a capacitor at their point of contact and the required area for a memory cell can be decreased by placing the plug electrode...	12/09/2003
6660625	Method of electroless plating copper on nitride barrier A method with three embodiments of manufacturing metal lines and solder bumps using electroless deposition techniques. The first embodiment uses a PdSix seed layer 50 for electroless deposition. The PdSix layer 50 does not require activation. A metal line...	12/09/2003
6642606	Method for producing siliconized polysilicon contacts in integrated semiconductor structures In the manufacture of integrated semiconductor structures, the problem frequently occurs that the resistance of polysilicon structures employed as interconnects must be selectively lowered. In order to reduce the resistance of a polysilicon structure, the...	11/04/2003
6620703	Method of forming an integrated circuit using an isolation trench having a cavity formed by reflowing a doped glass mask layer Isolation characteristics of an isolation trench can be enhanced. Elements to be isolated by an isolation trench (STI 2) are formed in active semiconductor regions shown by arrows 30 and 31 on a semiconductor substrate 1. The STI 2 is filled with SiOF....	09/16/2003
6614116	Buried digit line stack and process for making same A process of making a buried digit line stack is disclosed. The process includes forming a silicon-lean metal silicide first film over a polysilicon plug, followed by a silicide compound barrier second film. The silicide compound barrier second film is co...	09/02/2003
6599832	Silicide pattern structures and methods of fabricating the same Silicide interfaces for integrated circuits, thin film devices, and backend integrated circuit testing devices are formed using a barrier layer, such as titanium nitride, disposed over a porous, thin dielectric layer which is disposed between a silicon-co...	07/29/2003
6579614	Structure having refractory metal film on a substrate A method of treating structures (and the structure formed thereby), so as to prevent or retard the oxidation of a metal film, and/or prevent its delamination a substrate, includes providing a structure including a refractory metal film formed on a substra...	06/17/2003
6576510	Method of producing a semiconductor memory device using a self-alignment process According to the present invention, an overlay margin is secured for matching a wiring electrode 11 with a storage electrode 15 of a capacitor at their point of contact and the required area for a memory cell can be decreased by placing the plug electrode...	06/10/2003
6534408	Utilization of disappearing silicon hard mask for fabrication of semiconductor structures A method of forming structures in semiconductor devices through a buffer or insulator layer comprising the use of a silicon hard mask between a patterned resist layer for etching the structures and an underlying barrier layer. The silicon hard mask acts a...	03/18/2003
6528888	Integrated circuit and method An integrated circuit. The circuit includes a memory cell array including wordlines 201 formed on a substrate and bitlines 200 and capacitors 203 formed over the wordlines. The bitlines have a first thickness and pitch. The circuit also includes circuits ...	03/04/2003
6521505	Manufacturing method of semiconductor device In forming transistor electrodes, after a polysilicon film is formed, RF plasma etching is applied to the surface thereof to remove a natural oxidation film on the surface of the polysilicon film....	02/18/2003
6522001	Local interconnect structures and methods for making the same The present invention provides methods of forming local interconnect structures for integrated circuits. A representative embodiment includes depositing a silicon source layer over a substrate having at least one topographical structure thereon. The silic...	02/18/2003
6461963	Utilization of disappearing silicon hard mask for fabrication of semiconductor structures A method of forming structures in semiconductor devices through a buffer or insulator layer comprising the use of a silicon hard mask between a patterned resist layer for etching the structures and an underlying barrier layer. The silicon hard mask acts a...	10/08/2002
6451694	Control of abnormal growth in dichloro silane (DCS) based CVD polycide WSix films In a process for mitigating and/or eliminating the abnormal growth of underlying polysilicon in dichloro silane-based CVD polycide WSix films, a first technique conducts the deposition of the underlying polysilicon layer at a temperature that substantiall...	09/17/2002
6436816	Method of electroless plating copper on nitride barrier A method with three embodiments of manufacturing metal lines and solder bumps using electroless deposition techniques. The first embodiment uses a PdSix seed layer 50 for electroless deposition. The PdSix layer 50 does not require ac...	08/20/2002
6436805	Local interconnect structures and methods for making the same The present invention provides methods of forming local interconnect structures for integrated circuits. A representative embodiment includes depositing a silicon source layer over a substrate having at least one topographical structure thereon. The silic...	08/20/2002
6429455	Method to enhance the formation of nucleation sites on silicon structures and an improved silicon structure A method to enhance the formation of nucleation sites on at least one narrow silicon structure comprises the step: forming at least one nucleation region (206/208): masking the at least one narrow silicon structure (202) with a mask (302); treating the at...	08/06/2002
6410428	Nitride deposition on tungsten-polycide gate to prevent abnormal tungsten silicide oxidation A method of forming a non-oxidized WSix layer on a semiconductor wafer, including the following steps. A semiconductor wafer having a silicon substrate is provided within a CVD tool. A WSix layer is formed over the silicon substrate....	06/25/2002
6410420	Method of fabricating silicide pattern structures Silicide interfaces for integrated circuits, thin film devices, and backend integrated circuit testing devices are formed using a barrier layer, such as titanium nitride, disposed over a porous, thin dielectric layer which is disposed between a silicon-co...	06/25/2002
6410392	Method of producing MOS transistor The surface of a silicon substrate is sputter-etched so that silicon clusters sputtered out form a silicon film on a side wall spacer. Then, a metal film of cobalt, titanium or the like is built up on the entire surface. Thereafter, silicidizing process i...	06/25/2002
6406743	Nickel-silicide formation by electroless Ni deposition on polysilicon The present invention provides a method of manufacturing a nickel-silicide technology for polysilicon interconnects. Nickel 40 is deposited on polysilicon 30 using a electroless process. Using a rapid thermal anneal process, Ni 40 is transformed to NiSi a...	06/18/2002
6403480	Process for manufacturing semiconductor device A gate oxide layer 11 and a poly-silicon layer 12 are formed on a silicon substrate 10. A tungsten silicide (WSi) layer that includes dopant is formed by a sputtering method or CVD as the metal silicide layer. This layer is designated a first wiring patte...	06/11/2002
6399492	Ruthenium silicide processing methods The invention includes methods of processing ruthenium silicide. In one implementation, a ruthenium silicide processing method sequentially includes forming ruthenium silicide over front and back sides of a semiconductor substrate. The backside ruthenium ...	06/04/2002
6388296	CMOS self-aligned strapped interconnection An CMOS interconnection method that permits small source/drain surface areas has been provided. The interconnection is applicable to both strap and via type connections. The surface areas of the small source/drain regions are extended into neighboring fie...	05/14/2002
6387803	Method for forming a silicide region on a silicon body The invented method produces a silicide region on a silicon body that is useful for a variety of purposes, including the reduction of the electrical contact resistance to the silicon body or an integrated electronic device formed thereon. The invented met...	05/14/2002
6376368	Method of forming contact structure in a semiconductor device A method of forming a contact structure in a semiconductor device is provided. In this method, a semiconductor layer, an ohmic metal layer, and a barrier metal layer are formed on the surface of a semiconductor substrate on which a metal contact hole has ...	04/23/2002
6359301	Semiconductor device and method of manufacturing the same A semiconductor device comprising a first connecting plug for bit contact and a second connecting plug for storage node contact buried in a first inter-layer insulating layer covering the transistor and projecting from the transistor. The bit line is buri...	03/19/2002
6355549	Method of forming polycide structures A method of forming a polycide structure in accordance with the present invention includes forming a polysilicon layer on a surface. A refractory metal silicide portion of the polycide structure is formed on the polysilicon layer and the polysilicon porti...	03/12/2002

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Class 257/E21.296 - Of metal-silicide layer (EPO)