Class 257/E21.293 - Of silicon nitride (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.292. This
No. of patents: 407
Last issue date: 10/21/2008

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Number	Title	Issue Date
7439117	Method for designing a micro electromechanical device with reduced self-actuation A method is described for designing a micro electromechanical device in which the risk of self-actuation of the device in use is reduced. The method includes locating a first conductor in a plane and locating a second conductor with its collapsible portion at a pred...	10/21/2008
7432184	Integrated PVD system using designated PVD chambers A method for making a film stack containing one or more metal-containing layers and a substrate processing system for forming the film stack on a substrate are provided. The substrate processing system includes at least one transfer chamber coupled to at least one l...	10/07/2008
7432208	Method of manufacturing suspension structure A method of manufacturing a suspension structure including providing a substrate, forming a first photoresist pattern on the substrate, heating the first photoresist pattern to harden it as a sacrificial layer, forming a second photoresist pattern on the substrate a...	10/07/2008
7397074	RF field heated diodes for providing thermally assisted switching to magnetic memory elements An exemplary array of thermally-assisted magnetic memory structures includes a plurality of magnetic memory elements, each magnetic memory element being near a diode. A diode near a selected magnetic memory element can be heated by absorbing energy from a radio freq...	07/08/2008
7393731	Semiconductor device and method of manufacturing the same A silicon nitride film is formed between interlayer insulating films covering an upper surface of an element formed on a surface of a semiconductor layer. With this structure, a semiconductor device comprising an isolation insulating film of PTI structure, which sup...	07/01/2008
7393736	Atomic layer deposition of ZrHfSnOfilms as high k gate dielectrics The use of atomic layer deposition (ALD) to form a nanolaminate dielectric of zirconium oxide (ZrO2), hafnium oxide (HfO2) and tin oxide (SnO2) acting as a single dielectric layer with a formula of ZrXHfYSn...	07/01/2008
7384861	Strain modulation employing process techniques for CMOS technologies A method forms a semiconductor device comprising a modifiable strain inducing layer. A semiconductor body is provided. First and second regions of the semiconductor body are identified. A modifiable tensile strain inducing layer is formed over the device within the ...	06/10/2008
7384833	Stress liner for integrated circuits In one embodiment, a self-aligned contact (SAC) trench structure is formed through a dielectric layer to expose an active region of a MOS transistor. The SAC trench structure not only exposes the active region for electrical connection but also removes portions of a...	06/10/2008
7372090	Magnetic random access memory device and method of forming the same Example embodiments of the present invention disclose a semiconductor memory device and a method of forming a memory device. A semiconductor memory device may include a digit line disposed on a substrate, an intermediate insulating layer covering the digit line, a m...	05/13/2008
7368359	Method for manufacturing semiconductor substrate and semiconductor substrate A semiconductor substrate (100) is acquired by forming a mask with a target thickness on a major surface of a single-crystal silicon substrate, implanting oxygen ions to the major surface at a high temperature, forming a surface protection layer for blocking ...	05/06/2008
7365029	Method for silicon nitride chemical vapor deposition Embodiments of the invention generally provide a method for depositing a film containing silicon (Si) and nitrogen (N). In one embodiment, the method includes heating a substrate disposed in a processing chamber to a temperature less than about 650 degrees Celsius, ...	04/29/2008
7361613	Semiconductor device, manufacture and evaluation methods for semiconductor device, and process condition evaluation method A gate insulating film made of silicon oxynitride is disposed on the partial surface area of a semiconductor substrate. A gate electrode is disposed on the gate insulating film. Source and drain regions are disposed on both sides of the gate electrode. An existence ...	04/22/2008
7351668	Film formation method and apparatus for semiconductor process An insulating film is formed on a target substrate by CVD, in a process field to be selectively supplied with a first process gas containing a silane family gas, a second process gas containing a nitriding or oxynitriding gas, and a third process gas containing a ca...	04/01/2008
7351670	Method for producing silicon nitride films and process for fabricating semiconductor devices using said method Silicon nitride film is formed on a silicon wafer mounted in a boat in an LPCVD tool by feeding a silicon source (SiH2Cl2, SiCl4, Si2Cl6, etc.) from an injector and feeding a mixed gas of monomethylamine (CH	04/01/2008
7341903	Method of forming a field effect transistor having a stressed channel region A semiconductor structure comprises a transistor element formed in a substrate. A stressed layer is formed over the transistor element. The stressed layer has a predetermined compressive intrinsic stress having an absolute value of about 1 GPa or more. Due to this h...	03/11/2008
7332447	Method of forming a contact A method of forming a contact is provided. A substrate having at least two metal oxide semiconductor devices is provided and a gap is formed between the two devices. A first stress layer is formed over the substrate to cover the metal-oxide semiconductor devices and...	02/19/2008
7327009	Selective nitride liner formation for shallow trench isolation A method for forming a divot free nitride lined shallow trench isolation (STI) feature including providing a substrate including an STI trench extending through an uppermost hardmask layer into a thickness of the substrate exposing the substrate portions; selectivel...	02/05/2008
7309627	Method for fabricating a gate mask of a semiconductor device A nitride layer of the gate mask for the semiconductor device is deposited at a temperature higher than 750 deg. C so as to release hydrogen from the nitride layer. Alternatively, a nitride layer of the gate mask for the semiconductor device is deposited in a gas at...	12/18/2007
7306983	Method for forming dual etch stop liner and protective layer in a semiconductor device The present invention provides a semiconductor device having dual nitride liners, a silicide layer, and a protective layer beneath one of the nitride liners for preventing the etching of the silicide layer. A first aspect of the invention provides a method for use i...	12/11/2007
7303962	Fabricating method of CMOS and MOS device A complementary metal-oxide-semiconductor (CMOS) device comprising a substrate, a first type of metal-oxide-semiconductor (MOS) transistor, a second type of MOS transistor, an etching stop layer, a first stress layer and a second stress layer is provided. The substr...	12/04/2007
7300890	Method and apparatus for forming conformal SiNfilms A silicon nitride film formation method includes: Heating a substrate to be subjected to film formation to a substrate temperature; heating a wire to a wire temperature; supplying silane, ammonia, and hydrogen gases to the heating member; and forming a silicon nitri...	11/27/2007
7297641	Method to form ultra high quality silicon-containing compound layers Multiple sequential processes are conducted in a reaction chamber to form ultra high quality silicon-containing compound layers, including silicon nitride layers. In a preferred embodiment, a silicon layer is deposited on a substrate using trisilane as the silicon p...	11/20/2007
7294582	Low temperature silicon compound deposition Sequential processes are conducted in a batch reaction chamber to form ultra high quality silicon-containing compound layers, e.g., silicon nitride layers, at low temperatures. Under reaction rate limited conditions, a silicon layer is deposited on a substrate using...	11/13/2007
7259071	Semiconductor device with dual gate oxides A method for making a semiconductor device having a first active region and a second active region includes providing first and second isolation structures defining the first active region on a substrate. The first active region uses a first operational voltage, and...	08/21/2007
7247582	Deposition of tensile and compressive stressed materials A method of depositing tensile or compressively stressed silicon nitride on a substrate is described. Silicon nitride having a tensile stress with an absolute value of at least about 1200 MPa can be deposited from process gas comprising silicon-containing gas and ni...	07/24/2007
7241632	MTJ read head with sidewall spacers Following CMP, a magnetic tunnel junction stack may protrude through the oxide that surrounds it, making it susceptible to possible shorting to its sidewalls. The present invention overcomes this problem by depositing silicon nitride spacers on these sidewalls prior...	07/10/2007
7241690	Method for conditioning a microelectronics device deposition chamber The present invention provides, in one aspect, a method of conditioning a deposition chamber 100. An undercoat is placed on the walls of a deposition chamber 100 and a pre-deposition coat is deposited over the undercoat with a plasma gas mixture conducted at a high ...	07/10/2007
7232765	Utilization of a Ta-containing cap over copper to facilitate concurrent formation of copper vias and memory element structures Disclosed are methods for facilitating concurrent formation of copper vias and memory element structures. The methods involve forming vias over metal lines and forming copper plugs, wherein the copper plugs comprise memory element film forming copper plugs (memE cop...	06/19/2007
7223705	Ambient gas treatment of porous dielectric A method of modifying the porosity of a thickness of a layer of porous dielectric material having a surface and formed on a semiconductor substrate is provided by exposing the porous dielectric material to a sufficient temperature in the presence of a first gas to d...	05/29/2007
7214628	Plasma gate oxidation process using pulsed RF source power A method of fabricating a gate of a transistor device on a semiconductor substrate, includes the steps of placing the substrate in a vacuum chamber of a plasma reactor and introducing into the chamber a process gas that includes oxygen while maintaining a vacuum pre...	05/08/2007
7192855	PECVD nitride film A method for forming a semiconductor device is provided. In accordance with the method, a substrate (103) is provided, and a dielectric material (123) is formed on the substrate through plasma enhanced chemical vapor deposition (PECVD). The PECVD is co...	03/20/2007
7192888	Low selectivity deposition methods A deposition method includes forming a nucleation layer over a substrate, forming a layer of a first substance at least one monolayer thick chemisorbed on the nucleation layer, and forming a layer of a second substance at least one monolayer thick chemisorbed on the...	03/20/2007
7138317	Method of generating multiple oxides by plasma nitridation on oxide A method of forming multiple gate oxide thicknesses on active areas that are separated by STI isolation regions on a substrate. A first layer of oxide is grown to a thickness of about 50 Angstroms and selected regions are then removed. A second layer of oxide is gro...	11/21/2006
6924523	Semiconductor memory device and method for manufacturing the device A semiconductor memory device includes a semiconductor substrate and a support layer provided above the semiconductor substrate. Particles are formed on the support layer. A first electrode is provided on the support layer such that it covers the particles. The firs...	08/02/2005
6713780	Process using poly-buffered STI A method of providing a substantially planar trench isolation region having substantially rounded corners, said method comprising the steps of: (a) forming a film stack on a surface of a substrate, said film stack comprising an oxide layer, a polysilicon layer and a...	03/30/2004
6703282	Method of reducing NMOS device current degradation via formation of an HTO layer as an underlying component of a nitride-oxide sidewall spacer A method of forming an NMOS device with reduced device degradation, generated during a constant current stress, has been developed. The reduced device degradation is attributed to the use of a high temperature oxide (HTO), layer, used as an underlying com...	03/09/2004
6703283	Discontinuous dielectric interface for bipolar transistors A process for forming at least one interface region between two regions of semiconductor material. At least one region of dielectric material comprising nitrogen is formed in the vicinity of at least a portion of a boundary between the two regions of semi...	03/09/2004
6703708	Graded thin films Thin films are formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of imp...	03/09/2004
6703322	Method of forming multiple oxide layers with different thicknesses in a linear nitrogen doping process Multiple oxide layers with different thicknesses are formed on a semiconductor substrate with a silicon surface, having a first and second region. A sacrificial oxide layer is formed on the silicon surface to cover both the first region and the second reg...	03/09/2004
6704188	Ultra thin TCS (SiCL4) cell nitride for dram capacitor with DCS (SiH2Cl2) interface seeding layer A method for forming silicon nitride films on semiconductor devices is provided. In one embodiment of the method, a silicon-containing substrate is first exposed to a mixture of dichlorosilane (DCS) and a nitrogen-containing gas to desposit a thin silicon...	03/09/2004

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Class 257/E21.293 - Of silicon nitride (EPO)