Bizarre Patents
A hand wearable body squeegee comprising a glove portion, a concave squeegee band, and a linear squeegee band.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7435677 | Method for fabricating semiconductor device A method for fabricating a semiconductor device includes: forming a first inter-layer insulation layer over a substrate where a plurality of first contact holes are formed; forming a conductive layer over the first inter-layer insulation layer to fill the first cont... | 10/14/2008 |
| 7432197 | Methods of patterning photoresist, and methods of forming semiconductor constructions The invention includes semiconductor constructions containing optically saturable absorption layers. An optically saturable absorption layer can be between photoresist and a topography, with the topography having two or more surfaces of differing reflectivity relati... | 10/07/2008 |
| 7432210 | Process to open carbon based hardmask A method of opening a carbon-based hardmask layer composed of amorphous carbon containing preferably at least 60% carbon and between 10 and 40% hydrogen. The hardmask is opened by plasma etching using an etching gas composed of H2, N2, and CO. ... | 10/07/2008 |
| 7416992 | Method of patterning a low-k dielectric using a hard mask By using a non-metallic hard mask for patterning low-k dielectric materials of advanced semiconductor devices, an enhanced degree of etch fidelity is obtained. The present invention may readily be applied to via first-trench last, trench first-via last schemes. ... | 08/26/2008 |
| 7413963 | Method of edge bevel rinse A method of edge bevel rinse. First, a wafer having a coating material layer disposed thereon is provided. A light beam is optically projected on the wafer to form a reference pattern. The reference pattern defines a central region, and a bevel region surrounding th... | 08/19/2008 |
| 7390738 | Fabrication of semiconductor devices using anti-reflective coatings Techniques are disclosed for fabricating a device using a photolithographic process. The method includes providing a first anti-reflective coating over a surface of a substrate. A layer which is transparent to a wavelength of light used during the photolithographic ... | 06/24/2008 |
| 7365021 | Methods of fabricating a semiconductor device using an organic compound and fluoride-based buffered solution Methods are provided for fabricating a semiconductor device that include the steps of: sequentially forming a metal interconnection and a protecting layer on a semiconductor substrate; forming a contact hole on the protecting layer; isolating the contact hole by for... | 04/29/2008 |
| 7306955 | Method of performing a double-sided process A method of performing a double-sided process is provided. First, a wafer having a structural pattern disposed on the front surface is provided. Following that, a plurality of front scribe lines are defined on the structural pattern, and a filling layer is filled in... | 12/11/2007 |
| 7282440 | Integrated circuit contact A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices so manufactured. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of ... | 10/16/2007 |
| 7271098 | Method of fabricating a desired pattern of electronically functional material Provided is a method forming a desired pattern of electronically functional material 3 on a substrate 1. The method comprises the steps of: creating a first layer of patterning material 2 on the substrate whilst leaving areas of the substrate ex... | 09/18/2007 |
| 7268397 | Thermal dissipation structures for finfets A fin-type field effect transistor has an insulator layer above a substrate and a fin extending above the insulator layer. The fin has a channel region, and source and drain regions. A gate conductor is positioned over the channel region. The insulator layer include... | 09/11/2007 |
| 7247555 | Method to control dual damascene trench etch profile and trench depth uniformity A method of forming trench openings in a dual damascene trench and via etch process by using a two component hard mask layer, termed a bi-layer, over different intermetal dielectrics, IMD, to solve dual damascene patterning problems, such as, fencing and sub-trench ... | 07/24/2007 |
| 7226873 | Method of improving via filling uniformity in isolated and dense via-pattern regions An isotropic-diffusion filling method uses a thermal process on a result structure comprising a photoresist layer and an organic material layer to create a cross-linking layer there between, which minimizes step height differences between isolated and dense via-patt... | 06/05/2007 |
| 7208407 | Flash memory cells with reduced distances between cell elements An anti-reflective coating (ARC) is formed over the various layers involved in a cell fabrication process. The ARC is selectively etched such that the edges of the etched areas of the ARC slope downward at an angle determined by the thickness of the ARC. The etching... | 04/24/2007 |
| 7141474 | Fabrication method of a nonvolatile semiconductor memory A method of fabricating a nonvolatile semiconductor memory including the steps of: sequentially forming a gate insulating layer and a first conductive layer of a floating gate on a semiconductor substrate; depositing an inter-gate insulating layer; forming an openin... | 11/28/2006 |
| 7135398 | Reliable low-k interconnect structure with hybrid dielectric An advanced back-end-of-line (BEOL) interconnect structure having a hybrid dielectric is disclosed. The inter-layer dielectric (ILD) for the via level is preferably different from the ILD for the line level. In a preferred embodiment, the via-level ILD is formed of ... | 11/14/2006 |
| 7015552 | Dual work function semiconductor structure with borderless contact and method of fabricating the same A dual work function semiconductor structure with borderless contact and method of fabricating the same are presented. The structure may include a field effect transistor (FET) having a substantially cap-free gate and a conductive contact to a diffusion adjacent to ... | 03/21/2006 |
| 6703304 | Dual damascene process using self-assembled monolayer and spacers A method of fabricating a trench on an integrated circuit having first and second insulative layers includes providing a layer of material over the insulative layers; forming a first self-assembled monolayer on the layer of material; etching the first sel... | 03/09/2004 |
| 6699784 | Method for depositing a low k dielectric film (K>3.5) for hard mask application A method for depositing a silicon oxycarbide hard mask on a low k dielectric layer is provided. Substrates containing a silicon oxycarbide hard mask on a low k dielectric layer are also disclosed. The silicon oxycarbide hard mask may be formed by a proces... | 03/02/2004 |
| 6699792 | Polymer spacers for creating small geometry space and method of manufacture thereof In forming an opening or space in a substrate, a layer of photoresist is provided on the substrate, and the photoresist is patterned to provide photoresist bodies having respective adjacent sidewalls. A polymer layer is provided on the resulting structure... | 03/02/2004 |
| 6696759 | Semiconductor device with diamond-like carbon layer as a polish-stop layer A semiconductor structure includes a diamond-like carbon layer as a polish-stop for patterning a metal level into an inter-level dielectric substrate in a damascene process flow. The semiconductor structure includes a substrate having a dielectric layer f... | 02/24/2004 |
| 6696366 | Technique for etching a low capacitance dielectric layer Techniques for etching through a low capacitance dielectric layer in a plasma processing chamber are disclosed. The techniques uses an etch chemistry that includes N2, O2, and a hydrocarbon. By etching the low capacitance dielectric ... | 02/24/2004 |
| 6696363 | Method of and apparatus for substrate pre-treatment The present invention relates generally to a method and apparatus for converting a precursor material, preferably organometallic, to a film, preferably metal-containing, that is adherent to at least a portion of a substrate. Both method and apparatus incl... | 02/24/2004 |
| 6693038 | Method for forming electrical contacts through multi-level dielectric layers by high density plasma etching A method for forming within a dielectric layer upon a substrate within a microelectronics fabrication a series of contact via holes etched through the dielectric layer to multi-level contact layers employing reactive plasma etching methods to form the ser... | 02/17/2004 |
| 6693345 | Semiconductor wafer assemblies comprising photoresist over silicon nitride materials In one aspect, the invention includes a semiconductor processing method, comprising: a) providing a silicon nitride material having a surface; b) forming a barrier layer over the surface of the material, the barrier layer comprising silicon and nitrogen; ... | 02/17/2004 |
| 6689682 | Multilayer anti-reflective coating for semiconductor lithography A multilayer electrically conductive stack is formed in a semiconductor device prior to one step of photolithography. In this multilayer electrically conductive stack, alternate layers of the stack contain materials that differ in their refractive indices... | 02/10/2004 |
| 6689693 | Methods for utilization of disappearing silicon hard mask for fabrication of semiconductor structures A method of forming structures in semiconductor devices through a buffer or insulator layer comprises the use of a silicon hard mask between a patterned resist layer for etching the structures and an underlying barrier layer. The silicon hard mask acts as... | 02/10/2004 |
| 6680258 | Method of forming an opening through an insulating layer of a semiconductor device An opening through an insulating layer between a first layer and a second layer of a semiconductor device is formed where the second layer is a polysilicon or amorphous silicon hard mask layer. The polysilicon or amorphous silicon hard mask layer is etche... | 01/20/2004 |
| 6677661 | Semiconductive wafer assemblies In one aspect, the invention includes a semiconductor fabrication process, comprising: a) providing a substrate; b) forming a layer of silicon nitride over the substrate, the layer having a thickness; and c) enriching a portion of the thickness of the sil... | 01/13/2004 |
| 6677240 | Method for patterning dense and isolated features on semiconductor devices According to one embodiment of the invention, a method of forming a semiconductor device is provided. The method includes providing a first mask that defines a densely populated plurality of hole patterns. The first mask overlies a layer of dielectric mat... | 01/13/2004 |
| 6677255 | Method for removing fences without reduction of ONO film thickness A method of manufacturing a semiconductor device including providing a first layer, forming a layer of stacked oxide-nitride-oxide layer over the first layer, depositing a first silicon layer over the layer of stacked oxide-nitride-oxide layer, providing ... | 01/13/2004 |
| 6673719 | Method for etching using a multilevel hard mask A method for physical etching using a multilevel hard mask. A substrate having a multilayer structure thereon is provided. A BPSG layer, a masking material layer and a patterned photoresist layer are sequentially formed on the multilayer structure, wherei... | 01/06/2004 |
| 6670288 | Methods of forming a layer of silicon nitride in a semiconductor fabrication process In one aspect, the invention includes a semiconductor fabrication process, comprising: a) providing a substrate; b) forming a layer of silicon nitride over the substrate, the layer having a thickness; and c) enriching a portion of the thickness of the sil... | 12/30/2003 |
| 6664011 | Hole printing by packing and unpacking using alternating phase-shifting masks A new method is provided for the creation of contact holes. The DOF and MEF of closely packed holes can be improved using Alternating Phase Shifting Mask (Alt PSM) for the exposure of the holes. However, Alt PSM are dependent on hole density or hole separ... | 12/16/2003 |
| 6664180 | Method of forming smaller trench line width using a spacer hard mask An exemplary method of forming trench lines includes providing a photoresist pattern over an anti-reflective coating (ARC) layer where the ARC layer is deposited over a layer of material; etching the ARC layer according to the photoresist pattern to form ... | 12/16/2003 |
| 6664177 | Dielectric ARC scheme to improve photo window in dual damascene process This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically, to improve the photolithography processing window of a multi-layered dual damascene process by using a dielectric anti-reflective c... | 12/16/2003 |
| 6660624 | Method for reducing fluorine induced defects on a bonding pad surface A method for reducing a fluorine contamination level on a semiconductor wafer process surface including providing a semiconductor wafer surface having a process surface including an uppermost polyimide containing layer; reactive ion etching the process su... | 12/09/2003 |
| 6660645 | Process for etching an organic dielectric using a silyated photoresist mask A process for forming a semiconductor device may comprise forming an organic dielectric layer on a substrate, forming a protective layer on the organic dielectric layer, forming a photoresist mask on the protective layer, and silyating the photoresist mas... | 12/09/2003 |
| 6656837 | Method of eliminating photoresist poisoning in damascene applications A method is provided for processing a substrate including treating a surface of a dielectric layer comprising silicon and carbon by exposing the dielectric layer comprising silicon and carbon to a plasma of an inert gas, and depositing a photoresist on th... | 12/02/2003 |
| 6656532 | Layered hard mask and dielectric materials and methods therefor A damascene structure includes a hard mask layer that is applied in a liquid phase to a line dielectric layer. Contemplated hard mask layers comprise a Si--N bond and are densified such that the etch resistivity of the hard mask layer is greater than the ... | 12/02/2003 |
