Class 257/E21.256 - By dry-etching (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.255. This
No. of patents: 383
Last issue date: 10/14/2008

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Number	Title	Issue Date
7435663	Methods for dicing a released CMOS-MEMS multi-project wafer Simple but practical methods to dice a CMOS-MEMS multi-project wafer are proposed. On this wafer, micromachined microstructures have been fabricated and released. In a method, a photoresist is spun on the full wafer surface, and this photoresist is thick enough to c...	10/14/2008
7419902	Method of manufacture of semiconductor integrated circuit In a process for the manufacture of a semiconductor integrated circuit device having an inlaid interconnect structure by embedding a conductor film in a recess, such as a trench or hole, formed in an organic insulating film which constitutes an interlevel dielectric...	09/02/2008
7416973	Method of increasing the etch selectivity in a contact structure of semiconductor devices By providing an additional silicon dioxide based etch stop layer, a corresponding etch process for forming contact openings for directly connecting polysilicon lines and active areas may be controlled in a highly reliable manner. In another aspect, the etch selectiv...	08/26/2008
7413963	Method of edge bevel rinse A method of edge bevel rinse. First, a wafer having a coating material layer disposed thereon is provided. A light beam is optically projected on the wafer to form a reference pattern. The reference pattern defines a central region, and a bevel region surrounding th...	08/19/2008
7381622	Method for forming embedded strained drain/source regions based on a combined spacer and cavity etch process By patterning a spacer layer stack and etching a cavity in an in situ etch process, the process complexity, as well as the uniformity, during the formation of embedded strained semiconductor layers may be significantly enhanced. In an initial phase, the spacer layer...	06/03/2008
7344993	Low-pressure removal of photoresist and etch residue A method is provided for plasma ashing to remove photoresist remnants and etch residues formed during preceding plasma etching of dielectric layers. The ashing method uses a two-step plasma process involving a hydrogen-containing gas, where low or zero bias is appli...	03/18/2008
7344927	Method and apparatus for manufacturing active matrix device including top gate type TFT A method and an apparatus are provided for manufacturing an active matrix device including a top gate type TFT. A manufacturing process of the top gate type TFT includes the steps of forming an oxide film on the inner wall of a CVD processing chamber and arranging a...	03/18/2008
7341935	Alternative interconnect structure for semiconductor devices A semiconductor interconnect structure includes an organic and/or photosensitive etch buffer layer disposed over a contact surface. The structure further provides an interlevel dielectric formed over the etch buffer layer. A method for forming an interconnect struct...	03/11/2008
7326653	Method of preparation of organic optoelectronic and electronic devices and devices thereby obtained A method for preparing an organic electronic or optoelectronic device is described. The method comprises depositing a layer of fluorinated polymer on a substrate, patterning the layer of fluorinated polymer to form a relief pattern and depositing from solution a lay...	02/05/2008
7276448	Method for an integrated circuit contact A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect...	10/02/2007
7273817	Conditioning of a reaction chamber A method is provided for forming polymer on an interior surface of a reaction chamber. A polymer-forming gas is introduced into the chamber during the etching of a photoresist layer of a semiconductor wafer within the reaction chamber and the environment is regulate...	09/25/2007
7235479	Organic solvents having ozone dissolved therein for semiconductor processing utilizing sacrificial materials A method of fabricating a semiconductor device. The method comprises creating a via in a dielectric layer that is formed on a substrate, filling the via, and optionally, the surface of the dielectric layer with a sacrificial material, patterning a first photoresist ...	06/26/2007
7232763	Method of manufacturing semiconductor device A method of manufacturing a semiconductor device includes subjecting a semiconductor wafer, which includes a copper layer formed above a semiconductor substrate and covered with an insulating film, to a dry etching using a fluorocarbon gas to partially remove the in...	06/19/2007
7232768	Hydrogen plasma photoresist strip and polymeric residue cleanup process for low dielectric constant materials A method (100) of fabricating an electronic device (200) formed on a semiconductor wafer. The method forms a layer (215) of a first material in a fixed position relative to the wafer. The first material has a dielectric constant less than 3.6. T...	06/19/2007
7208407	Flash memory cells with reduced distances between cell elements An anti-reflective coating (ARC) is formed over the various layers involved in a cell fabrication process. The ARC is selectively etched such that the edges of the etched areas of the ARC slope downward at an angle determined by the thickness of the ARC. The etching...	04/24/2007
7179752	Dry etching method A dry etching method involves plasma etching an organic anti-reflecting coating film through a mask layer made of photoresist and having a predetermined pattern by using an etching gas of CF4 and O2. The method allows an organic anti-reflecting...	02/20/2007
7179751	Hydrogen plasma photoresist strip and polymeric residue cleanup process for low dielectric constant materials A method (100) of fabricating an electronic device (200) formed on a semiconductor wafer. The method forms a layer (215) of a first material in a fixed position relative to the wafer. The first material has a dielectric constant less than 3.6. T...	02/20/2007
6699784	Method for depositing a low k dielectric film (K>3.5) for hard mask application A method for depositing a silicon oxycarbide hard mask on a low k dielectric layer is provided. Substrates containing a silicon oxycarbide hard mask on a low k dielectric layer are also disclosed. The silicon oxycarbide hard mask may be formed by a proces...	03/02/2004
6696366	Technique for etching a low capacitance dielectric layer Techniques for etching through a low capacitance dielectric layer in a plasma processing chamber are disclosed. The techniques uses an etch chemistry that includes N2, O2, and a hydrocarbon. By etching the low capacitance dielectric ...	02/24/2004
6693043	Method for removing photoresist from low-k films in a downstream plasma system A unique photoresist strip sequence using a downstream plasma system is described. The sequence can include a RF directional plasma alone, downstream plasma alone or combine both RF plasma and downstream plasma together. The process sequence can be a sing...	02/17/2004
6686228	Semiconductor device and manufacturing method thereof It is an object of the present invention to provide a manufacturing method of semiconductor device whereby the number of processes is decreased due to simultaneously forming a contact hole in a lamination film of different material and film thickness (ino...	02/03/2004
6686293	Method of etching a trench in a silicon-containing dielectric material Disclosed herein is a method of etching a trench in a silicon-containing dielectric material, in the absence of a trench etch-stop layer, where the silicon-containing dielectric material has a dielectric constant of about 4 or less. The method comprises e...	02/03/2004
6686296	Nitrogen-based highly polymerizing plasma process for etching of organic materials in semiconductor manufacturing A method of etching an organic antireflective film layer underlying a patterned resist layer on a semiconductor substrate by contacting the exposed organic film with a fluorocarbon and nitrogen etchant in the presence of a plasma-generated energy and remo...	02/03/2004
6679997	Organic insulation film formation method The present invention enables reduction of a film thickness of a protection film so as to eliminate destruction caused by stress of the protection film; to increase a film thickness of an organic insulation film so as to exhibit the function of the organi...	01/20/2004
6680164	Solvent free photoresist strip and residue removal processing for post etching of low-k films A photoresist or a residue of the photoresist may by removed by the hydrogen and water plasma mixture. The process may be performed at a temperature range between about 150° C. and about 450° C., preferably about 250° C., and a power range between abou...	01/20/2004
6680255	Plasma etching methods A plasma etching method includes forming polymer material over at least some internal surfaces of a plasma etch chamber and forming polymer material over at least some surfaces of a semiconductor wafer received within the plasma etch chamber. Substantiall...	01/20/2004
6673685	Method of manufacturing semiconductor devices A process for economical and efficient fabrication of gate electrodes no larger than 50 nm, which is beyond the limit of exposure, is characterized by gate-electrode trimming and mask trimming with high resist selectivity which are performed in combinatio...	01/06/2004
6673725	Semiconductor device and method of manufacturing the same The present invention relates to a semiconductor device manufacturing method for forming an interlayer insulating film having a low dielectric constant by coating a copper wiring. The low dielectric constant insulating film is formed by reaction of a plas...	01/06/2004
6669858	Integrated low k dielectrics and etch stops A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in depos...	12/30/2003
6670276	Plasma processing method A wafer W is placed on a lower electrode 106 provided inside a processing chamber 102 of a plasma processing apparatus 100. A film constituted an organic polysiloxane, which is a Low-K material is formed at the wafer W. Plasma is generated inside the proc...	12/30/2003
6670265	Low K dielectic etch in high density plasma etcher An integrated circuit wafer and a manufacturing process for etching low K spin-on dielectrics such as HSQ in a High Density Plasma etch reactor utilizes roof and wall temperature to improve across-the-wafer uniformity, and a mixture of C4F8 and C2F6 etch ...	12/30/2003
6667219	Methods for forming void regions, dielectric regions and capacitor constructions In one aspect, the invention includes a method of forming a void region associated with a substrate, comprising: a) providing a substrate; b) forming a sacrificial mass over the substrate; c) subjecting the mass to hydrogen to convert a component of the m...	12/23/2003
6667243	Etch damage repair with thermal annealing A method of manufacturing a semiconductor device etches a feature on a substrate in accordance with a photoresist mask. The photoresist mask is removed by plasma etching. Laser thermal annealing is performed to vaporize polymer residue created during the ...	12/23/2003
6667244	Method for etching sidewall polymer and other residues from the surface of semiconductor devices A method for removing organic and inorganic residues or polymers from the surface of semiconductor devices, with a combination of etchant gasses including water vapor generated using a catalytic moisture generator or CMG. The water vapor is generated by i...	12/23/2003
6664199	Coating liquid for forming a silica group coating film having a small dielectric constant A coating liquid for forming a silica group coating film having a dielectric constant equal to or less than 3.2, comprises a condensation product which is obtained through hydrolysis of trialkoxysilane within an organic solvent under an acid catalysis; an...	12/16/2003
6664194	Photoexposure method for facilitating photoresist stripping There is first provided a substrate 10 and a target layer 12. There is then formed upon the target layer a patterned positive photoresist layer 14. There is then processed the target layer while employing the patterned positive photoresist layer as a mask...	12/16/2003
6660700	Formulations including a 1,3-dicarbonyl compound chelating agent and copper corrosion inhibiting agents for stripping residues from semiconductor substrates containing copper structures A semiconductor wafer cleaning formulation, including 2-98% wt. organic amine, 0-50% wt. water, 0.1-60% wt. 1,3-dicarbonyl compound chelating agent, 0-25% wt. of additional different chelating agent(s), 0.5-40% wt. nitrogen-containing carboxylic acid or a...	12/09/2003
6660624	Method for reducing fluorine induced defects on a bonding pad surface A method for reducing a fluorine contamination level on a semiconductor wafer process surface including providing a semiconductor wafer surface having a process surface including an uppermost polyimide containing layer; reactive ion etching the process su...	12/09/2003
6656832	Plasma treatment method for fabricating microelectronic fabrication having formed therein conductor layer with enhanced electrical properties A method for fabricating a microelectronic fabrication provides for forming a patterned conductor layer into a via defined by a pair of dielectric layers. Within the method, the via is plasma treated prior to forming therein the patterned conductor layer ...	12/02/2003
6656532	Layered hard mask and dielectric materials and methods therefor A damascene structure includes a hard mask layer that is applied in a liquid phase to a line dielectric layer. Contemplated hard mask layers comprise a Si--N bond and are densified such that the etch resistivity of the hard mask layer is greater than the ...	12/02/2003

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Class 257/E21.256 - By dry-etching (EPO)