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| Number | Title | Issue Date |
| 7432210 | Process to open carbon based hardmask A method of opening a carbon-based hardmask layer composed of amorphous carbon containing preferably at least 60% carbon and between 10 and 40% hydrogen. The hardmask is opened by plasma etching using an etching gas composed of H2, N2, and CO. ... | 10/07/2008 |
| 7422943 | Semiconductor device capacitors with oxide-nitride layers and methods of fabricating such capacitors Capacitors having upper electrodes that include a lower electrode, a dielectric layer and an upper electrode that includes a conductive metal nitride layer and a doped polysilicon germanium layer are provided. At least part of the conductive metal nitride layer is o... | 09/09/2008 |
| 6693020 | Method of preparing copper metallization die for wirebonding A method of preparing a semiconductor wafer having a integrated circuits formed on it that have pads formed of copper includes the steps of removing oxide from the copper pads and then the vacuum packing the wafer in a shock-proof container. The oxide may... | 02/17/2004 |
| 6690091 | Damascene structure with reduced capacitance using a boron carbon nitride passivation layer, etch stop layer, and/or cap layer A damascene structure with reduced capacitance dielectric stacking comprise a passivation, a first dielectric, an etch stop, a second dielectric and a cap layer over a first conductive layer formed on a semiconductor. The passivation, the etch stop, and t... | 02/10/2004 |
| 6682944 | Semiconductor device manufacturing method There is provided a semiconductor device manufacturing method having a ferroelectric or high-dielectric capacitor, which comprises the steps of forming an underlying insulating film over a semiconductor substrate, forming a first conductive film on the un... | 01/27/2004 |
| 6656748 | FeRAM capacitor post stack etch clean/repair The present invention is directed to a method of forming an FeRAM integrated circuit, which includes performing a capacitor stack etch to define the FeRAM capacitor. The method comprises etching a PZT ferroelectric layer with a high temperature BCl3 | 12/02/2003 |
| 6656840 | Method for forming silicon containing layers on a substrate A method for forming a microelectronics device is disclosed. In one embodiment, the method includes depositing a conductive structure on a substrate. A first layer comprising silicon and nitrogen is formed on the substrate. A second layer comprising silic... | 12/02/2003 |
| 6656787 | Method for fabricating non-volatile memories A method for fabricating a semiconductor component includes the steps of applying an electrode material and a metal-oxide-containing layer on a substrate surface and selectively etching the electrode material and the metal-oxide-containing layer for formi... | 12/02/2003 |
| 6649466 | Method of forming DRAM circuitry In part, disclosed are semiconductor processing methods, methods of depositing a tungsten comprising layer over a substrate, methods of depositing a tungsten nitride comprising layer over a substrate, methods of depositing a tungsten silicide comprising l... | 11/18/2003 |
| 6635498 | Method of patterning a FeRAM capacitor with a sidewall during bottom electrode etch A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the patterning of a top electrode layer and a dielectric layer to form a capacitor stack structure having sidewalls associated therewith. Prior to patterning the bottom e... | 10/21/2003 |
| 6624076 | Semiconductor device and method for fabricating the same First, a pattern of electrodes or interconnects is formed on a semiconductor substrate. Next, a first insulating film, which will be dry-etched at a relatively high rate and exhibit relatively high planarity, is deposited over the substrate as well as ove... | 09/23/2003 |
| 6623579 | Methods and apparatus for fluidic self assembly Methods and apparatuses for assembling a structure onto a substrate. A method according to one aspect of the invention includes dispensing a slurry onto a substrate wherein the slurry includes a first plurality of elements, each of which is designed to ma... | 09/23/2003 |
| 6624462 | Dielectric film and method of fabricating the same A Pt/Ti film is formed on a substrate, and the Pt/Ti film is patterned in to a bottom electrode. Subsequently, a SrTiO3 film, that is, a dielectric film, is formed on the substrate by sputtering using a mixture of an Ar gas, an O2 ga... | 09/23/2003 |
| 6617250 | Methods of depositing a layer comprising tungsten and methods of forming a transistor gate line In part, disclosed are semiconductor processing methods, methods of depositing a tungsten comprising layer over a substrate, methods of depositing a tungsten nitride comprising layer over a substrate, methods of depositing a tungsten silicide comprising l... | 09/09/2003 |
| 6613687 | Reverse reactive ion patterning of metal oxide films The invention provides a method for making thin film metal oxide actuator device. According to the method a first conductive layer is deposited on a silicon substrate. Next a thin film metal oxide layer is deposited on the first conductive layer. A negati... | 09/02/2003 |
| 6613680 | Method of manufacturing a semiconductor device A method of manufacturing a semiconductor device provided with a first insulating film and a barrier film on a conductive region and an opening portion in the first insulating film and the barrier film, the method comprising the steps of: forming a first ... | 09/02/2003 |
| 6576526 | Darc layer for MIM process integration A new processing sequence is provided for the creation of a MIM capacitor. The process starts with the deposition of a first layer of metal. Next are deposited listed, a thin layer of metal, a layer of insulation, a second layer of metal and a layer of An... | 06/10/2003 |
| 6547934 | Reduction of metal oxide in a dual frequency etch chamber The invention generally provides an apparatus and a method of removing metal oxides, particularly copper oxides and aluminum oxides, from a substrate surface. Primarily, the invention eliminates sputtering of copper oxide from the bottom of an interconnec... | 04/15/2003 |
| 6544833 | Semiconductor memory device and manufacturing method thereof A semiconductor memory device is manufactured by uniformly forming an epitaxial capacitor layer on the whole surface of a single-crystal semiconductor layer, finely dividing the capacitor layer into individual capacitors by etching, using the individual c... | 04/08/2003 |
| 6534809 | Hardmask designs for dry etching FeRAM capacitor stacks An embodiment of the instant invention is a ferroelectric capacitor formed over a semiconductor substrate, the ferroelectric capacitor comprising: a bottom electrode formed over the semiconductor substrate, the bottom electrode comprised of a bottom elect... | 03/18/2003 |
| 6528429 | Methods of etching insulative materials, of forming electrical devices, and of forming capacitors In one aspect, the invention encompasses a method of etching insulative materials which comprise complexes of metal and oxygen. The insulative materials are exposed to physical etching conditions within a reaction chamber and in the presence of at least o... | 03/04/2003 |
| 6511896 | Method of etching a substantially amorphous TA2O5 comprising layer In part, disclosed are semiconductor processing methods, methods of depositing a tungsten comprising layer over a substrate, methods of depositing a tungsten nitride comprising layer over a substrate, methods of depositing a tungsten silicide comprising l... | 01/28/2003 |
| 6511918 | Method of structuring a metal-containing layer The processes allow structuring of a metal-containing layer. The metal-containing layer is etched, using an etching mask, in a plasma-assisted etching gas atmosphere at a temperature of over 130° C. and in the presence of at least one halogen compound an... | 01/28/2003 |
| 6503792 | Method for fabricating a patterned metal-oxide-containing layer The damage to edge sections which occurs during the patterning of a metal-oxide-containing layer can be compensated by the deposition of an annealing layer and a subsequent heat treatment step through which a material flow takes place from the annealing l... | 01/07/2003 |
| 6497992 | Process for manufacturing semiconductor integrated circuit device In order that reaction products of low vapor pressure may be prevented from being deposited on the side wall of a predetermined pattern when this pattern is to be formed by dry-etching a Pt film or a PZT film, a resist mask 54 having a rounded outer perip... | 12/24/2002 |
| 6495413 | Structure for masking integrated capacitors of particular utility for ferroelectric memory integrated circuits A method for fabricating integrated capacitors, of particular utility in forming a ferroelectric capacitor array for a ferroelectric memory integrated circuits, begins with provision of a substrate. The substrate is typically a partially-processed CMOS in... | 12/17/2002 |
| 6485988 | Hydrogen-free contact etch for ferroelectric capacitor formation An embodiment of the instant invention is a method of forming a conductive contact to a top electrode (308 and 310 of FIG. 4d) of a ferroelectric capacitor comprised of a bottom electrode (304 of FIG. 4d) situated under the top electrode and a ferroelectr... | 11/26/2002 |
| 6465346 | Conducting line of semiconductor device and manufacturing method thereof using aluminum oxide layer as hard mask A conducting line of a semiconductor device using an aluminum oxide layer as a hard mask, and a method of forming the conducting line. The conducting line, such as a gate line or a bit line of a semiconductor device, includes a conductive layer formed on ... | 10/15/2002 |
| 6454956 | Structuring method A method for structuring at least one layer to be structured. First, a mask is applied to the layer and the layer is structured using the mask. After the structuring step, the mask is then removed, while leaving behind redepositions of the material of the... | 09/24/2002 |
| 6448179 | Method for fabricating semiconductor device The present invention discloses a method for fabricating a semiconductor device. In particular, methods of the present invention produces a contact plug which is larger than the presumed contact region. As a result, the acceptable process error margin for... | 09/10/2002 |
| 6436838 | Method of patterning lead zirconium titanate and barium strontium titanate In an embodiment of the present invention, a method is provided of patterning PZT layers or BST layers. For example, a PZT layer or a BST layer is plasma etched through a high-temperature-compatible mask such as a titanium nitride (TiN) mask, using a plas... | 08/20/2002 |
| 6432779 | Selective removal of a metal oxide dielectric A method for forming a semiconductor device is disclosed in which a metal oxide gate dielectric layer is formed over a substrate. A gate electrode is then formed over the metal oxide layer thereby exposing a portion of the metal oxide layer. The exposed p... | 08/13/2002 |
| 6319767 | Method to eliminate top metal corner shaping during bottom metal patterning for MIM capacitors via plasma ashing and hard masking technique A method for fabricating a metal-insulator-metal capacitor wherein top metal corner shaping during patterning is eliminated is described. An insulating layer is provided overlying a semiconductor substrate. A composite metal stack is formed comprising a f... | 11/20/2001 |
| 6315913 | Structuring method A method for structuring at least one layer to be structured. Initially, a mask is applied to the layer and the layer is structured using the mask. After the structuring step, the mask is then removed, while leaving behind redepositions of the material of... | 11/13/2001 |
| 6300202 | Selective removal of a metal oxide dielectric A method for forming a semiconductor device is disclosed in which a metal oxide gate dielectric layer is formed over a substrate. A gate electrode is then formed over the metal oxide layer thereby exposing a portion of the metal oxide layer. The exposed p... | 10/09/2001 |
| 6277760 | Method for fabricating ferroelectric capacitor Method for fabricating a ferroelectric capacitor, including the steps of (1) foxing an etch stopper formed of any one of TiO.sub.2 and RuO.sub.2 a lower electrode, a ferroelectric layer, an upper electrode, and an etch mask layer formed of any one of Ti, ... | 08/21/2001 |
| 6165891 | Damascene structure with reduced capacitance using a carbon nitride, boron nitride, or boron carbon nitride passivation layer, etch stop layer, and/or cap layer A method and structure for forming a damascene structure with reduced capacitance by forming one or more of: the passivation layer, the etch stop layer, and the cap layer using a low dielectric constant material comprising carbon nitride, boron nitride, o... | 12/26/2000 |
| 6153514 | Self-aligned dual damascene arrangement for metal interconnection with low k dielectric constant materials and nitride middle etch stop layer A method of forming a self-aligned dual damascene structure in a semiconductor device arrangement forms a first low k dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. A nitride etch stop layer is formed... | 11/28/2000 |
| 6100201 | Method of forming a semiconductor memory device A method of forming a capacitor by forming a dielectric layer over a bottom electrode layer, forming a top electrode layer over the dielectric layer to form laminations of the bottom electrode layer, the dielectric layer and the top electrode layer, and s... | 08/08/2000 |
| 6057081 | Process for manufacturing semiconductor integrated circuit device In order that reaction products of low vapor pressure may be prevented from being deposited on the side wall of a predetermined pattern when this pattern is to be formed by dry-etching a Pt film or a PZT film, a resist mask 54 having a rounded outer perip... | 05/02/2000 |
