Class 257/E21.252 - By dry-etching (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.251. This
No. of patents: 1140
Last issue date: 10/28/2008

«First «Previous1 2 3 4 5 6 7 8 9 10 11 Next»Last»

Number	Title	Issue Date
7442649	Etch with photoresist mask A method for etching a dielectric layer over a substrate is provided. A photoresist mask is formed over the dielectric layer. The substrate is placed in a plasma processing chamber. An etchant gas comprising NF3 is provided into the plasma chamber. A plas...	10/28/2008
7434719	Addition of Dto Hto detect and calibrate atomic hydrogen formed by dissociative electron attachment A method of detecting and calibrating dry fluxing metal surfaces of one or more components to be soldered by electron attachment using a gas mixture of reducing gas comprising hydrogen and deuterium, comprising the steps of: a) providing one or more components to be...	10/14/2008
7423307	CMOS image sensor and method for fabricating the same Provided are a CMOS image sensor in which microlenses are formed in a remaining space in a patterned light shielding layer to improve image sensor characteristics and to protect the microlenses during packaging, and a method of fabricating the same. The CMOS image s...	09/09/2008
7419847	Method for forming metal interconnection of semiconductor device A method for forming a metal interconnection of a semiconductor device avoids over-etching and under-etching through the use of the “self-stop” function of a nitridation layer, to prevent the occurrence of openings and voids in a copper interconnection and to ob...	09/02/2008
7416988	Semiconductor device and fabrication process thereof A method of fabricating a semiconductor device includes the steps of modifying a damaged layer containing carbon and formed at a semiconductor surface by exposing the damaged layer to oxygen radicals to form a modified layer, and removing the modified layer by a wet...	08/26/2008
7416973	Method of increasing the etch selectivity in a contact structure of semiconductor devices By providing an additional silicon dioxide based etch stop layer, a corresponding etch process for forming contact openings for directly connecting polysilicon lines and active areas may be controlled in a highly reliable manner. In another aspect, the etch selectiv...	08/26/2008
7413963	Method of edge bevel rinse A method of edge bevel rinse. First, a wafer having a coating material layer disposed thereon is provided. A light beam is optically projected on the wafer to form a reference pattern. The reference pattern defines a central region, and a bevel region surrounding th...	08/19/2008
7413960	Method of forming floating gate electrode in flash memory device A method of forming a floating gate electrode in a flash memory device. The method includes forming an isolation film in an inactive region so that a step with a predetermined thickness can be generated between an active region and the inactive region, which are def...	08/19/2008
7387738	Removal of surface oxides by electron attachment for wafer bumping applications The present invention relates to a method for removing metal oxides from a substrate surface. In one particular embodiment, the method comprises: providing a substrate, a first, and a second electrode that reside within a target area; passing a gas mixture comprisin...	06/17/2008
7381622	Method for forming embedded strained drain/source regions based on a combined spacer and cavity etch process By patterning a spacer layer stack and etching a cavity in an in situ etch process, the process complexity, as well as the uniformity, during the formation of embedded strained semiconductor layers may be significantly enhanced. In an initial phase, the spacer layer...	06/03/2008
7354867	Etch process for improving yield of dielectric contacts on nickel silicides The embodiments of the invention generally relate to an etching process, and more particularly to an etch processing for improving the yield of dielectric contacts on nickel silicides. An oxygen-free feedgas is used in an etching process to reduce or eliminate resid...	04/08/2008
7351643	Method of manufacturing a semiconductor device Even though photolithography with a diameter of 0.20 μm or less is employed, a contact hole having a tapered shape with a required width including a positioning tolerance can be formed in a narrower gap between the gate electrodes. A method forms a minute contact h...	04/01/2008
7352064	Multiple layer resist scheme implementing etch recipe particular to each layer Methods of forming a metal line and/or via critical dimension (CD) in a single or dual damascene process on a semiconductor substrate, and the resist scheme implemented, are disclosed. The method includes forming a multiple layer resist scheme including a first plan...	04/01/2008
7338903	Sequential reducing plasma and inert plasma pre-treatment method for oxidizable conductor layer A method for forming a barrier layer upon a copper containing conductor layer employs a hydrogen containing plasma treatment of the copper containing conductor layer followed by an argon plasma treatment of the copper containing conductor layer. The barrier layer ma...	03/04/2008
7303952	Method for fabricating doped polysilicon lines A method of fabricating polysilicon lines and polysilicon gates, the method of including: providing a substrate; forming a dielectric layer on a top surface of the substrate; forming a polysilicon layer on a top surface of the dielectric layer; implanting the polysi...	12/04/2007
7282441	De-fluorination after via etch to preserve passivation Novel interconnect structures possessing a dense OSG material for 90 nm and beyond BEOL technologies in which a low power density oxygen-based de-fluorination plasma process is utilized to increase NBLoK selectivity are presented. These BEOL interconnect structures ...	10/16/2007
7268397	Thermal dissipation structures for finfets A fin-type field effect transistor has an insulator layer above a substrate and a fin extending above the insulator layer. The fin has a channel region, and source and drain regions. A gate conductor is positioned over the channel region. The insulator layer include...	09/11/2007
7265042	Method for fabricating semiconductor device with gate spacer The present invention relates to a method for fabricating a semiconductor device with gate spacers. The method includes the steps of: forming a plurality of gate structures on a substrate; forming an insulation layer on the gate structures and the substrate; and etc...	09/04/2007
7253116	High ion energy and reative species partial pressure plasma ash process A high ion energy and high pressure O2/CO-based plasma for ashing field photoresist material subsequent to via-level damascene processing. The optimized plasma ashing process is performed at greater than approximately 300 mT pressure and ion energy greate...	08/07/2007
7232768	Hydrogen plasma photoresist strip and polymeric residue cleanup process for low dielectric constant materials A method (100) of fabricating an electronic device (200) formed on a semiconductor wafer. The method forms a layer (215) of a first material in a fixed position relative to the wafer. The first material has a dielectric constant less than 3.6. T...	06/19/2007
7232720	Method for fabricating a semiconductor device having an insulation film with reduced water content A semiconductor device having a self-aligned contact hole is formed by providing a side wall oxide film on a gate electrode, covering the gate electrode and the side wall oxide film by an oxide film and further covering the oxide film by a nitride film, wherein the ...	06/19/2007
7229915	Method for manufacturing semiconductor device A first insulating film, a second insulating film, a third insulating film, an antireflective film, and a resist film are formed in this order on a lower-layer wiring. After dry etching the third insulating film and the second insulating film, using the resist film ...	06/12/2007
7208407	Flash memory cells with reduced distances between cell elements An anti-reflective coating (ARC) is formed over the various layers involved in a cell fabrication process. The ARC is selectively etched such that the edges of the etched areas of the ARC slope downward at an angle determined by the thickness of the ARC. The etching...	04/24/2007
7179751	Hydrogen plasma photoresist strip and polymeric residue cleanup process for low dielectric constant materials A method (100) of fabricating an electronic device (200) formed on a semiconductor wafer. The method forms a layer (215) of a first material in a fixed position relative to the wafer. The first material has a dielectric constant less than 3.6. T...	02/20/2007
7169682	Method for manufacturing semiconductor device A method for manufacturing a semiconductor device comprising: a first step of successively forming a silicon oxide film and a silicon nitride film on a silicon substrate, followed by forming a silicon nitride oxide film or a multil...	01/30/2007
7141474	Fabrication method of a nonvolatile semiconductor memory A method of fabricating a nonvolatile semiconductor memory including the steps of: sequentially forming a gate insulating layer and a first conductive layer of a floating gate on a semiconductor substrate; depositing an inter-gate insulating layer; forming an openin...	11/28/2006
7138340	Method for fabricating semiconductor device without damaging hard mask during contact formation process Disclosed is a method for fabricating a semiconductor device without damaging a hard mask of a conductive structure. The method includes the steps of: forming a plurality of conductive structures on a substrate, each conductive structure including a conductive layer...	11/21/2006
6846757	Dielectric layer for a semiconductor device and method of producing the same A semiconductor device includes a low dielectric constant insulating film exhibiting an Si—H Fourier Transform Infrared (FTIR) doublet defined by a first and a second peak, wherein the first peak is located at a higher wave number than the second peak, and wherein...	01/25/2005
6703297	Method of removing inorganic gate antireflective coating after spacer formation Various methods of manufacturing are disclosed. In one aspect, a method of manufacturing is provided that includes forming an anti-reflective coating on a structure on a substrate. A first spacer and a second spacer are formed adjacent to the structure. T...	03/09/2004
6700202	Semiconductor device having reduced oxidation interface A method and apparatus for reducing oxidation of an interface of a semiconductor device thereby improving adhesion of subsequently formed layers and/or devices is disclosed. The semiconductor device has at least a first layer and a second layer wherein th...	03/02/2004
6699795	Gate etch process A method of making a semiconductor structure includes etching an anti-reflective coating layer at a pressure of 10 millitorr or less; etching a nitride layer with a first nitride etch plasma having a first F:C ratio; and etching the nitride layer with a s...	03/02/2004
6696366	Technique for etching a low capacitance dielectric layer Techniques for etching through a low capacitance dielectric layer in a plasma processing chamber are disclosed. The techniques uses an etch chemistry that includes N2, O2, and a hydrocarbon. By etching the low capacitance dielectric ...	02/24/2004
6693003	Semiconductor device and manufacturing method of the same In a semiconductor device, formed are a lower capacitor electrode on an element isolation film on a silicon substrate, a capacitor insulating film and an upper capacitor electrode. A silicon oxide film is formed on the entire surface of the silicon substr...	02/17/2004
6692580	Method of cleaning a dual damascene structure A method of cleaning a dual damascene structure. A first metal layer, a cap layer, and a dielectric layer are formed on a substrate in sequence. Then a dual damascene opening is formed in the dielectric layer and the cap layer, exposing the first metal la...	02/17/2004
6693047	Method for recycling semiconductor wafers having carbon doped low-k dielectric layers A method for removing at least one carbon doped oxide layer over a surface to recycle the semiconductor process wafer including providing a semiconductor wafer including a process surface including at least one carbon doped silicon oxide layer; oxidizing ...	02/17/2004
6693042	Method for etching a dielectric layer formed upon a barrier layer A method for etching a dielectric layer formed upon a barrier layer with an etch chemistry including Cx Hy Fz, in which xࣙ2, yࣙ2, and zࣙ2 is provided. Such an etch chemistry may be selective to the barrier layer. For...	02/17/2004
6693040	Method for cleaning the contact area of a metal line A method for cleaning a contact area of a metal line wherein a nitride barrier layer is formed on a sidewall of an insulating interlayer within the contact area by introducing the nitrogen-based radical to the contact area, whereby it is possible to preve...	02/17/2004
6693038	Method for forming electrical contacts through multi-level dielectric layers by high density plasma etching A method for forming within a dielectric layer upon a substrate within a microelectronics fabrication a series of contact via holes etched through the dielectric layer to multi-level contact layers employing reactive plasma etching methods to form the ser...	02/17/2004
6689699	Method for manufacturing a semiconductor device using recirculation of a process gas There is disclosed a semiconductor processing apparatus comprising a process chamber treating a substrate, a process gas feeder feeding a process gas to the process chamber, a first vacuum pump exhausting the process chamber, a second vacuum pump inhaling...	02/10/2004
6690084	Semiconductor device including insulation film and fabrication method thereof A semiconductor device including an insulation film superior in insulation characteristic is obtained. Boron ions are introduced by ion implantation into an organic SOG film with a silicon nitride film formed on the organic SOG film. By this boron implant...	02/10/2004

«First «Previous1 2 3 4 5 6 7 8 9 10 11 Next»Last»

PatentStorm

Quotables

PatentStorm News

Class 257/E21.252 - By dry-etching (EPO)