Class 257/E21.231 - Using mask (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.215. This subclass
No. of patents: 121
Last issue date: 10/28/2008

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Number	Title	Issue Date
7442640	Semiconductor device manufacturing methods Methods of manufacturing a semiconductor device including a high-voltage device region and a low-voltage device region are provided. An illustrated method includes forming, on a substrate, a gate pattern for a high-voltage device and a low-voltage device; implanting...	10/28/2008
7419906	Method for manufacturing a through conductor A method of manufacturing a through conductor that penetrates from an upper surface of a silicon substrate to its lower surface. The through conductor is manufactured in steps which provide a first conductor which extends in the direction of thickness of the silicon...	09/02/2008
7416987	Semiconductor device and method of fabricating the same According to the present invention, there is a provided a semiconductor device fabrication method having, forming a mask material in a surface portion of a semiconductor substrate, and forming a step having a projection by using the mask material; forming a dielectr...	08/26/2008
7410854	Method of making FUSI gate and resulting structure Generally disclosed is a method of a device comprising forming a polysilicon stack including a first and a second polysilicon layer with an intervening etch stop layer, wherein the first polysilicon layer height is at least one third a height of the polysilicon stac...	08/12/2008
7410891	Method of manufacturing a superjunction device A partially manufactured semiconductor device includes a semiconductor substrate. The device includes a first oxide layer formed on the substrate, with a mask placed over the oxide-covered substrate, a plurality of first trenches and at least one second trench etche...	08/12/2008
7405144	Method for manufacturing probe card A method for manufacturing a probe card is provided. A first inactive layer, a first patterned photoresist layer and a first metal layer are sequentially formed on a substrate. The first metal layer has first through holes exposing a portion of the first patterned p...	07/29/2008
7384874	Method of forming hardmask pattern of semiconductor device A method of forming a hardmask pattern over a semiconductor device semiconductor device includes forming a first hardmask layer over a semiconductor substrate. First and second structures are formed over the first hardmask layer, the first and second structures form...	06/10/2008
7384833	Stress liner for integrated circuits In one embodiment, a self-aligned contact (SAC) trench structure is formed through a dielectric layer to expose an active region of a MOS transistor. The SAC trench structure not only exposes the active region for electrical connection but also removes portions of a...	06/10/2008
7368359	Method for manufacturing semiconductor substrate and semiconductor substrate A semiconductor substrate (100) is acquired by forming a mask with a target thickness on a major surface of a single-crystal silicon substrate, implanting oxygen ions to the major surface at a high temperature, forming a surface protection layer for blocking ...	05/06/2008
7329606	Semiconductor device having nanowire contact structures and method for its fabrication A semiconductor device having small electrical contacts to impurity doped regions and a method for fabrication of such a device are provided. In accordance with one embodiment of the invention the semiconductor device comprises a semiconductor substrate having a dop...	02/12/2008
7285497	Mask, method for manufacturing a mask, method for manufacturing an electro-optical device, and electronic equipment A mask includes a silicon member, and a portion defining an opening penetrating the silicon member; and the corner of the opening is rounded. ...	10/23/2007
7271094	Multiple shadow mask structure for deposition shadow mask protection and method of making and using same The present invention is a multi-layer shadow mask and method of use thereof. The multi-layer shadow mask includes a sacrificial mask bonded to a deposition mask. The sacrificial mask provides protection against an accumulation of evaporant on the deposition mask wh...	09/18/2007
7241634	Semiconductor device and method for producing the same The invention provides a semiconductor device having less defectives in shape of a patterned wiring layer even in a case of having a wiring layer for which patterning is required to be carried out over a longer period of etching time, and a method for producing the ...	07/10/2007
7226872	Lightly doped drain MOS transistor A method of forming a MOS transistor in an upper surface of a semiconductor substrate. A gate oxide layer covers the upper surface of the substrate. A gate stack including one or more thin film layers covers the gate oxide layer. A gate electrode pattern is partiall...	06/05/2007
7109110	Method of manufacturing a superjunction device A partially manufactured semiconductor device includes a semiconductor substrate. The device includes a first oxide layer formed on the substrate, with a mask placed over the oxide-covered substrate, a plurality of first trenches and at least one second trench etche...	09/19/2006
6660643	Etching of semiconductor wafer edges A novel method of etching a plurality of semiconductor wafers is provided which comprises assembling said plurality of wafers in a stack, and subjecting said stack of wafers to dry etching using a relatively high density plasma which is produced at atmosp...	12/09/2003
6649996	In situ and ex situ hardmask process for STI with oxide collar application A method or process for etching a trench in an IC structure is disclosed. The IC structure might be comprised of a plurality of different component materials arranged proximate to one another, all of which need to be etched down to a target level. A first...	11/18/2003
6426175	Fabrication of a high density long channel DRAM gate with or without a grooved gate The present invention lengthens gate conductors used in memory chips to limit leakage current, while still allowing the overall size of cells to remain the same. The channel length for each gate is increased by decreasing the size of spaces between gates....	07/30/2002
6162702	Self-supported ultra thin silicon wafer process A silicon wafer 2 has an ultra thin central portion 2 that is supported by a circumferential rim 3 of thicker silicon. The central region is thinned by conventional means using conventional removal apparatus. As an alternative method, the central portion ...	12/19/2000
6093511	Method of manufacturing semiconductor device The present invention relates to a method of manufacturing a semiconductor device including a step of exposing a resist by use of an exposure mask. An object of the present invention is to facilitate a level adjustment of the reticle and thus automaticall...	07/25/2000
6069091	In-situ sequential silicon containing hard mask layer/silicon layer plasma etch method A method for etching a silicon layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a blanket silicon layer. There is then formed upon the ...	05/30/2000
5965005	Mask for porous silicon formation The present invention provides a method for forming porous silicon, which includes the steps of: a) providing a silicon substrate; b) growing a GaAs layer on the silicon substrate; c) defining a pattern for the GaAs layer by a photolithography process and...	10/12/1999
5914280	Deep trench etch on bonded silicon wafer A quick, deep, clean two step trench process for an SOI/bonded wafer substrate 100 is disclosed. A first isotropic plasma etch using SF6 is made through an opening 40 in the photoresist layer on device layer 16. A second anisotropic plasma etch using SF6 ...	06/22/1999
5907771	Reduction of pad erosion Improved technique of forming trench capacitors without causing excessive erosion at the edges of the array region resulting from polishing. The erosion is reduced by providing a block mask to protect the array region while partially removing a portion of...	05/25/1999
5776817	Method of forming a trench structure in a semiconductor device The invention relates to a method of forming trenches having different depths in a substrate of an IC using different refractory metal layers. The depths of the trenches can be changed by controlling the thicknesses of the refractory metal layers. The pro...	07/07/1998
5738757	Planar masking for multi-depth silicon etching A planar masking process for multi-depth etching of a silicon wafer wherein more than one etch depth is photolithographically patterned prior to etching the wafer and while the wafer still has a planar surface. A plurality of layers of masking material ar...	04/14/1998
5695658	Non-photolithographic etch mask for submicron features A non-photolithographic, physical patterning process, which is useful for selectively etching of a substrate, is provided. The process comprises electrostatically charging liquid droplets which are selectively etchable with respect to the substrate, dispe...	12/09/1997
5693182	Method for damage etching the back side of a semiconductor disk having a protected front side A method for making large scale integrated circuits on a disklike semiconductor substrate includes grinding a disk thin enough to be able to be sawn apart into individual chips. A damage zone caused by the grinding on a back side of the wafer is removed b...	12/02/1997
5610090	Method of making a FET having a recessed gate structure A Field Effect Transistor having a recessed gate comprises a substrate, a source electrode and a drain electrode, a recessed channel region formed over an area of the semiconductor substrate between the source electrode and the drain electrode, and a gate...	03/11/1997
5554256	Method of manufacturing a semiconductor device having a semiconductor body with field insulation regions formed by grooves filled with insulating material A method of manufacturing a semiconductor device comprising a semiconductor body (1) with field insulation regions (14) formed by grooves (10; 24) filled with an insulating material (13) is disclosed. The grooves (10; 24) are etched into the semiconductor...	09/10/1996
5550088	Fabrication process for a self-aligned optical subassembly A method is disclosed for forming a self-aligned optical subassembly for supporting an optical fiber and associated optical component(s). In particular, sequential masking layer/silicon substrate etch operations are performed so as to etch, in series, the...	08/27/1996
5478438	Method of etching semiconductor substrate A method of performing anisotropic etching more than once with respect to a semiconductor substrate (1) is provided with the steps of performing first-time anisotropic etching by using a first etching mask (2) so as to form a first anisotropically etched ...	12/26/1995
5470767	Method of making field effect transistor A semiconductor device having a gate electrode having a leg with two mutually offset portions is formed by successively depositing on a semiconductor substrate an amorphous material and a crystalline metal layer. A portion of the crystalline metal layer i...	11/28/1995
5258332	Method of manufacturing semiconductor devices including rounding of corner portions by etching A method for rounding the corners of trench formed on the silicon substrate with metal, metal silicide or polycrystalline silicon thin film or the step portions of lead layers is provided. The steps of rounding are performed by chemical dry etching using ...	11/02/1993
5244822	Method of fabricating bipolar transistor using self-aligned polysilicon technology In a bipolar transistor, having a micronized structure for a high-speed LSI, which is fabricated by a self-alignment technology, a barrier insulating film is buried in a portion around an emitter layer so as to be deeper than a junction level between an a...	09/14/1993
5096842	Method of fabricating bipolar transistor using self-aligned polysilicon technology In a bipolar transistor, having a micronized structure for a high-speed LSI, which is fabricated by a self-alignment technology, a barrier insulating film is buried in a portion around an emitter layer so as to be deeper than a junction level between an a...	03/17/1992
5001080	Method for producing a monolithically integrated optoelectronic device A semiconductor device including a substrate having a low substrate surface formed in the substrate with a first gentle slope from the substrate surface; a single crystalline layer formed on the low substrate surface nearly level with the substrate surfac...	03/19/1991
4970578	Selective backside plating of GaAs monolithic microwave integrated circuits A technique for etching tub structures and vias on the backside of a wafer comprised of gallium arsenide and for providing a planar surface on said backside of the gallium arsenide wafer is described. The tubs are formed by providing a layer of resist ove...	11/13/1990
4952521	Process for fabricating a semiconductor device with selective growth of a metal silicide A metal or metal silicide layer (37) is selectively grown on a nucleating layer (28) with a predetermined pattern on an insulating layer and on a substrate below an opening in an insulating layer, to form a metal or metal silicide electrode in contact wit...	08/28/1990
4946804	Aperture forming method A method of forming through-holes in a multi-level interconnect system in which a layer of photo-resist is spun over a masking layer prior to mask-etching so that when the photo-resist is exposed and developed some remains in the bottom of through holes f...	08/07/1990

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Class 257/E21.231 - Using mask (EPO)