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| Number | Title | Issue Date |
| 7416940 | Methods for fabricating flash memory devices Methods for fabricating a flash memory device are provided. A method comprises forming a plurality of gate stacks overlying a substrate. Each gate stack comprises a charge trapping layer and a control gate. The control gate is a first distance from the substrate. Ad... | 08/26/2008 |
| 7402492 | Method of manufacturing a memory device having improved erasing characteristics In a method of manufacturing a memory device having improved erasing characteristics, the method includes sequentially forming a tunneling oxide layer, a charge storing layer, and a blocking oxide layer on a semiconductor substrate; annealing the semiconductor subst... | 07/22/2008 |
| 7391078 | Non-volatile memory and manufacturing and operating method thereof A non-volatile memory is provided. A substrate having a plurality of trenches and a plurality of select gates is provided. The trenches are arranged in parallel and extend in a first direction. Each of the select gates is disposed on the substrate between two adjace... | 06/24/2008 |
| 7371694 | Semiconductor device fabrication method and fabrication apparatus The flatness of the surface of a Si substrate is requested as the present gate length is miniaturized. The present invention is a semiconductor device fabrication method for flattening a silicon surface by continuously supplying a high-temperature fluoride ammonium ... | 05/13/2008 |
| 7368356 | Transistor with doped gate dielectric A transistor and method of manufacture thereof. A semiconductor workpiece is doped before depositing a gate dielectric material. Using a separate anneal process or during subsequent anneal processes used to manufacture the transistor, dopant species from the doped r... | 05/06/2008 |
| 7365729 | Field sequential LCD device and color image display method thereof In a liquid crystal display device, a field sequential liquid crystal display device includes a liquid crystal panel having an upper substrate, a lower substrate and a liquid crystal layer therebetween; a backlight device under the liquid crystal panel for irradiati... | 04/29/2008 |
| 7307280 | Memory devices with active and passive doped sol-gel layers The present memory device includes first and second electrodes, an active layer; and a passive layer, the active and passive layers being between the first and second electrodes, with at least one of the active layer and passive layer being a doped a sol-gel. ... | 12/11/2007 |
| 7285463 | Method of fabricating non-volatile memory A method of fabricating a non-volatile memory is described. A plurality of first memory units having gaps between each other is formed over a substrate. Insulating spacers are formed on the sidewalls of the first memory units. A composite layer is formed on the subs... | 10/23/2007 |
| 7238599 | Multi-state NROM device An array of NROM flash memory cells configured to store at least two bits per four F2. Split vertical channels are generated along each side of adjacent pillars. A single control gate is formed over the pillars and in the trench between the pillars. The s... | 07/03/2007 |
| 7229888 | Capacitor with hafnium oxide and aluminum oxide alloyed dielectric layer and method for fabricating the same The present invention relates to a capacitor having a hafnium oxide and aluminum oxide alloyed dielectric layer and a method for fabricating the same. The capacitor includes: a lower electrode; a dielectric layer formed on the lower electrode; and an upper electrode... | 06/12/2007 |
| 7196008 | Aluminum oxide as liner or cover layer to spacers in memory device For fabricating a memory device, spacers are formed to sides of word-line gates. In addition, aluminum oxide is formed as one of a liner layer or a cover layer to the spacers. The aluminum oxide has a chemical composition of Al2O3 for example. ... | 03/27/2007 |
| 7192830 | Method for fabricating a memory cell Silicon nanocrystals are applied as storage layer (6) and removed using spacer elements (11) laterally with respect to the gate electrode (5). By means of an implantation of dopant, source/drain regions (2) are fabricated in a self-aligne... | 03/20/2007 |
| 7141512 | Method of cleaning semiconductor device fabrication apparatus A semiconductor device fabrication apparatus is cleaned after a conductive layer is formed on a metal oxide layer of a substrate. The substrate is disposed on a heater in a process chamber of the apparatus, and the conductive layer is formed by introducing source ga... | 11/28/2006 |
| 7132302 | Method of increasing cell retention capacity of silicon nitride read-only-memory cell A method of increasing the cell retention capacity of a silicon nitride read-only-memory on a wafer. The method includes carrying out a baking process after performing the last plasma treatment of the wafer but before a wafer sort test. ... | 11/07/2006 |
| 7129135 | Nonvolatile semiconductor memory device and method for fabricating the same A first conductive film for forming a plurality of word lines is formed in a memory cell array formation region of a semiconductor substrate for a nonvolatile semiconductor memory device, and a second conductive film is formed in a semiconductor device formation reg... | 10/31/2006 |
| 7109078 | CMOS compatible process for making a charge trapping device A method of making an n-channel metal-insulator-semiconductor field-effect transistor (MISFET) that uses charge trapping for altering channel conductivity characteristics is disclosed. Other suitable and conventional processing steps are used to finalize completion ... | 09/19/2006 |
| 6693004 | Interfacial barrier layer in semiconductor devices with high-K gate dielectric material A semiconductor device and a process for fabricating the device, including, in one embodiment, a silicon substrate; a first interfacial barrier layer on the silicon substrate, in which the first interfacial barrier layer may include aluminum oxide, silico... | 02/17/2004 |
| 6677200 | Method of forming non-volatile memory having floating trap type device A method of forming a non-volatile memory having a floating trap-type device is disclosed in the present invention. In the method, a relatively thick thermal oxide layer is formed at a semiconductor substrate and patterned to leave a thick thermal oxide p... | 01/13/2004 |
| 6677213 | SONOS structure including a deuterated oxide-silicon interface and method for making the same A method for processing a semiconductor topography is provided, which includes diffusing deuterium across one or more interfaces of a silicon-oxide-nitride-oxide-silicon (SONOS) structure. In particular, the method may include diffusing deuterium across o... | 01/13/2004 |
| 6677204 | Multigate semiconductor device with vertical channel current and method of fabrication The present invention is a multibit nonvolatile memory and its method of fabrication. According to the present invention a silicon channel body having a first and second channel surface is formed. A charge storage medium is formed adjacent to the first ch... | 01/13/2004 |
| 6674138 | Use of high-k dielectric materials in modified ONO structure for semiconductor devices A process for fabrication of a semiconductor device including a modified ONO structure, including forming the modified ONO structure by providing a semiconductor substrate; forming a first oxide layer on the semiconductor substrate; depositing a layer com... | 01/06/2004 |
| 6664601 | Method of orperating a dual mode FET & logic circuit having negative differential resistance mode A process for operating a dual mode FET and a logic circuit to include a negative differential resistance (NDR) characteristic is disclosed. In a FET embodiment, an NDR characteristic is selectively enabled/disabled by biasing a body contact, thus permitt... | 12/16/2003 |
| 6642573 | Use of high-K dielectric material in modified ONO structure for semiconductor devices A process for fabrication of a semiconductor device including a modified ONO structure, comprising forming the modified ONO structure by providing a semiconductor substrate; forming a first dielectric material layer on the semiconductor substrate; deposit... | 11/04/2003 |
| 6643170 | Method for operating a multi-level memory cell A method for operating a memory cell of a multi-level NROM is described. The memory cell of the multi-level NROM comprises a nitride layer, wherein the nitride layer comprises a plurality of charge-trapping regions to store locally a plurality of charges ... | 11/04/2003 |
| 6642113 | Non-volatile memory capable of preventing antenna effect and fabrication thereof A non-volatile memory capable of preventing the antenna effect and the fabrication thereof are described. The non-volatile memory includes a word-line having a high resistance portion and a memory cell portion on a substrate and a charge trapping layer lo... | 11/04/2003 |
| 6639271 | Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same A method of fabricating a dual bit dielectric memory cell structure on a silicon substrate includes implanting buried bit lines within the substrate and fabricating a layered island on the surface of the substrate between the buried bit lines. The island ... | 10/28/2003 |
| 6632714 | Method for manufacturing semiconductor memory The present invention discloses the new structure with regard to a nonvolatile semiconductor memory which can store therein an information corresponding to a plurality of bits. The nonvolatile semiconductor memory according to the present invention has a ... | 10/14/2003 |
| 6627498 | Memory cell fabrication method and memory cell configuration The memory cell has a source region and a drain region in semiconductor material and, above a channel region between the source and drain regions, a three-layered layer structure with a storage layer between boundary layers and a gate electrode arranged t... | 09/30/2003 |
| 6620694 | Method of making non volatile memory with a protective metal line A non-volatile memory and the fabrication thereof are described. The non-volatile memory comprises a word-line on a substrate, a charge trapping layer between the word-line and the substrate, and a contact electrically connecting with the word-line over t... | 09/16/2003 |
| 6617204 | Method of forming the protective film to prevent nitride read only memory cell charging A method of forming a protective film to prevent a nitride read only memory is disclosed. In the method of the present invention, the protective layers are formed in the inter-level dielectrics (ILD)/inter-metal dielectrics (IMD) layer of the nitride read... | 09/09/2003 |
| 6617179 | Method and system for qualifying an ONO layer in a semiconductor device A method and system for qualifying an oxide-nitride-oxide (QNO) layer including a first oxide layer, a nitride layer and a control oxide layer in a semiconductor device is disclosed. The method and system including determining a first plurality of dielect... | 09/09/2003 |
| 6613632 | Fabrication method for a silicon nitride read-only memory A fabrication method for a read-only memory with a silicon nitride floating gate is provided. A first oxide layer and a silicon nitride layer are sequentially formed on a substrate. The silicon nitride layer and the first oxide layer are then patterned to... | 09/02/2003 |
| 6607957 | Method for fabricating nitride read only memory The present invention relates to a method for fabricating a nitride read only memory (NROM), comprising: forming a doped polysilicon layer over a substrate, defining the doped polysilicon layer by using a patterned mask layer to form a plurality of doped ... | 08/19/2003 |
| 6602805 | Method for forming gate dielectric layer in NROM In fabricating nitride read only memory, a zirconium oxide layer has high dielectric constant and a zirconium oxide layer is replaced conventional tunnel oxide layer. Zirconium oxide layer can increase coupling ratio of gate dielectric layer and reliabili... | 08/05/2003 |
| 6583007 | Reducing secondary injection effects A method for forming a non-volatile memory (NVM) device, the method including forming two diffusion areas in a substrate, said diffusion areas forming a channel therebetween, the channel being adapted to permit movement of primary electrons to at least on... | 06/24/2003 |
| 6580103 | Array of flash memory cells and data program and erase methods of the same The present invention relates to an array of flash memory cells whose unit cell includes a single transistor of MONOS/SONOS structure (Metal/poly-Silicon Oxide Nitride Oxide Semiconductor) and to data programming and erasing using the same. The array of t... | 06/17/2003 |
| 6580120 | Two bit non-volatile electrically erasable and programmable memory structure, a process for producing said memory structure and methods for programming, reading and erasing said memory structure A planar high-density EEPROM split gate memory structure, is formed using two poly-layers and chemical-mechanical-polishing processes. Stripes of contiguous poly lines, alternately formed in one of the two poly-layers, constitute the memory structure. Sou... | 06/17/2003 |
| 6566699 | Non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping A method of enhancing erasure of a cell having a non-conductive charge trapping layer, the cell having a gate generally over the charge trapping layer includes programming the cell to minimize the width of a trapping region within the charge trapping laye... | 05/20/2003 |
| 6552387 | Non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping An electrically erasable programmable read only memory (EEPROM) having a non conducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. The invention includes... | 04/22/2003 |
| 6548425 | Method for fabricating an ONO layer of an NROM The present invention fabricates an oxide-nitride-oxide (ONO) layer of an NROM. A first oxide layer is formed on the surface of the substrate of a semiconductor wafer. Then two CVD processes are performed to respectively form a first nitride layer and a s... | 04/15/2003 |
