Class 257/E21.209 - Making electrode structure comprising conductor-insulator-conuctor-insulator-semiconductor, e.g., gate stack for non-volatile memory (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.158. This subclass
No. of patents: 709
Last issue date: 10/14/2008

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Number	Title	Issue Date
7436019	Non-volatile memory cells shaped to increase coupling to word lines A non-volatile memory array has word lines coupled to floating gates, the floating gates having an upper portion that is adapted to provide increased surface area, and thereby, to provide increased coupling to the word lines. Shielding between floating gates is also...	10/14/2008
7435654	Analog capacitor having at least three high-k dielectric layers, and method of fabricating the same There are provided an analog capacitor having at least three high-k dielectric layers, and a method of fabricating the same. The analog capacitor includes a lower electrode, an upper electrode, and at least three high-k dielectric layers interposed between the lower...	10/14/2008
7432204	Wafer and the manufacturing and reclaiming methods thereof A wafer and the manufacturing and reclaiming methods thereof are disclosed. The wafer includes a semiconductor substrate and a protective layer formed on the surface of the semiconductor substrate. The reclaiming method of the wafer includes providing a wafer having...	10/07/2008
7429539	Nitriding method of gate oxide film A substrate processing method comprises the step of forming an oxide film on a silicon substrate surface, and introducing nitrogen atoms into the oxide film by exposing the oxide film to nitrogen radicals excited in plasma formed by a microwave introduced via a plan...	09/30/2008
7425482	Non-volatile memory device and method for fabricating the same A non-volatile memory device and a method for fabricating the same are provided. The method includes: forming a plurality of gate structures on a substrate, each gate structure including a first electrode layer for a floating gate; forming a first insulation layer c...	09/16/2008
7419870	Method of manufacturing a flash memory device Provided is a method of manufacturing a flash memory device. In the method, after forming a cell string and source/drain selection transistors, it forms a first oxide film in which a sidewall oxide film and a buffering oxide film are stacked, a nitride film, and a s...	09/02/2008
7416935	Method of manufacturing nonvolatile semiconductor memory device having adjacent selection transistors connected together A method of manufacturing a nonvolatile semiconductor memory device, including forming a gate insulating film, a first conductive layer providing floating gates and a mask, in that order, on a semiconductor substrate, forming a plurality of element-isolating regions...	08/26/2008
7410868	Method for fabricating a nonvolatile memory element and a nonvolatile memory element In a method for fabricating a nonvolatile memory element a substrate is provided, a nanomask structure is fabricated on the substrate and a self-assembled monolayer of an organic memory molecule is grown on the substrate on a region not covered by the nanomask struc...	08/12/2008
7396750	Method and structure for contacting two adjacent GMR memory bit A method and a structure are provided for improving the contact of two adjacent GMR memory bits. Two adjacent bit ends are connected by utilizing a single via. ...	07/08/2008
7396721	Method of fabricating a semiconductor device According to the present invention, there is provided a semiconductor device fabrication method comprising: forming a first insulating film on a semiconductor substrate; forming a first conductive layer on the firs...	07/08/2008
7396727	Transistor of semiconductor device and method for fabricating the same A transistor which may effectively control the short channel effect with a vertical transistor structure. This structure may prevent the degradation of a transistor's performance caused by the hot carrier effect. The transistor has a source region having a concentra...	07/08/2008
7391078	Non-volatile memory and manufacturing and operating method thereof A non-volatile memory is provided. A substrate having a plurality of trenches and a plurality of select gates is provided. The trenches are arranged in parallel and extend in a first direction. Each of the select gates is disposed on the substrate between two adjace...	06/24/2008
7384848	Method for forming non-volatile memory with inlaid floating gate A method for forming a non-volatile memory with inlaid floating gate is disclosed. The method comprises the following steps. A substrate having a pad dielectric layer and a first dielectric layer thereon is provided. Then a buried diffusion region is formed in the s...	06/10/2008
7381655	Mandrel/trim alignment in SIT processing Disclosed herein is an imaging method for patterning component shapes (e.g., fins, gate electrodes, etc.) into a substrate. By conducting a trim step prior to performing either an additive or subtractive sidewall image transfer process, the method avoids the formati...	06/03/2008
7374991	SONOS memory device having side gate stacks and method of manufacturing the same In a silicon-oxide-nitride-oxide-silicon (SONOS) memory device and a method of manufacturing the same, a SONOS memory device includes a semiconductor substrate, an insulating layer deposited on the semiconductor substrate, an active layer formed on a predetermined r...	05/20/2008
7368348	Methods of forming MOS transistors having buried gate electrodes therein Methods of forming field effect transistors having buried gate electrodes include the steps of forming a semiconductor substrate having a sacrificial gate electrode buried beneath a surface of the semiconductor substrate and then removing the sacrificial gate electr...	05/06/2008
7368341	Semiconductor circuit arrangement with trench isolation and fabrication method An explanation is given of, inter alia, a circuit arrangement containing a trench which penetrates through a charge-storing layer (18) and a doped semiconductor layer (14). The trench simultaneously fulfils a multiplicity of functions, namely an insula...	05/06/2008
7365383	Method of forming an EPROM cell and structure therefor An EPROM cell includes a control gate and a control transistor. A portion of the control transistor is formed as a portion of the control gate. ...	04/29/2008
7348241	Cell structure of EPROM device and method for fabricating the same Provided are a cell structure of an EPROM device and a method for fabricating the same. The cell structure includes a gate stack, which includes a first floating gate, an insulating pattern including a nitride layer, and a control gate that are sequentially stacked ...	03/25/2008
7338863	Semiconductor memory device and method of manufacturing the semiconductor memory device Example embodiments of the present invention disclose a non-volatile semiconductor memory device, which may include a dielectric layer having an enhanced dielectric constant. A tunnel oxide layer pattern and a floating gate may be sequentially formed on a substrate....	03/04/2008
7335940	Flash memory and manufacturing method thereof A method for manufacturing flash memory is provided. A tunneling dielectric layer, a conductive layer and a patterned mask layer that exposes a portion of the conductive layer are formed on a substrate. An oxide layer is formed on the exposed conductive layer so tha...	02/26/2008
7333362	Electrically erasable and programmable, non-volatile semiconductor memory device having a single layer of gate material, and corresponding memory plane The semiconductor memory device includes an electrically erasable programmable non-volatile memory cell having a single layer of gate material and including a floating-gate transistor and a control gate. The source, drain and channel regions of the floating-gate tra...	02/19/2008
7320915	Method of manufacturing flash memory device The present invention relates to a method of manufacturing a flash memory device. According to the method of manufacturing the flash memory device, a gate line is formed to have a structure in which a tunnel oxide film, a polysilicon layer for floating gate, dielect...	01/22/2008
7314797	Semiconductor device and its manufacturing method A semiconductor device is capable of being applied with both a positive and a negative voltage to its control gate, and writing to its memory requires a low voltage. A control gate is formed on a memory unit region of a field oxide film, and an inter-layer silicon o...	01/01/2008
7312498	Nonvolatile semiconductor memory cell and method of manufacturing the same A stacked-gate structure includes a tunnel insulation film, a floating gate electrode, an inter-electrode insulation film and a control gate electrode, which are stacked on a semiconductor substrate. The inter-electrode insulation film has a three-layer structure th...	12/25/2007
7307280	Memory devices with active and passive doped sol-gel layers The present memory device includes first and second electrodes, an active layer; and a passive layer, the active and passive layers being between the first and second electrodes, with at least one of the active layer and passive layer being a doped a sol-gel. ...	12/11/2007
7301194	Shrinkable and highly coupled double poly EEPROM with inverter A nonvolatile EEPROM cell having a double poly arrangement provides stored data without sense amplifiers, thereby reducing power requirements. The EEPROM cell has a floating gate in a first poly layer, and a control gate overlapping the floating gate in a second pol...	11/27/2007
7300886	Interlayer dielectric for charge loss improvement A method of manufacturing a memory device includes forming a first dielectric layer over a substrate and forming a charge storage element over the first dielectric layer. The method also includes forming a second dielectric layer over the charge storage element and ...	11/27/2007
7268090	Method of manufacturing flash memory device A method of manufacturing flash memory devices, comprises the steps of forming an oxide film on a semiconductor substrate, performing a pre-annealing process under N2 gas atmosphere, nitrifying the oxide film by performing a main annealing process under N...	09/11/2007
7259420	Multiple-gate device with floating back gate Disclosed is a multiple-gate transistor that includes a channel region and source and drain regions at ends of the channel region. A gate oxide is positioned between a logic gate and the channel region and a first insulator is formed between a floating gate and the ...	08/21/2007
7256091	Method of manufacturing a semiconductor device with a self-aligned polysilicon electrode In a method of manufacturing a semiconductor device, an isolation pattern is formed on a substrate. The isolation pattern includes an opening that exposes a portion of the substrate. A preliminary polysilicon layer is formed on the substrate and the isolation patter...	08/14/2007
7242621	Floating-gate MOS transistor with double control gate The present invention relates to a floating-gate MOS transistor, comprising drain and source regions implanted into a silicon substrate, a channel extending between the drain and source regions, a tunnel oxide, a floating gate, a gate oxide and a control gate extend...	07/10/2007
7242052	Non-volatile memory A stacked structure is formed over a substrate, and the stacked structure has a gate dielectric layer and a floating gate thereon. A first dielectric layer, a second dielectric layer and a third dielectric layer are respectively formed over the top and the sidewalls...	07/10/2007
7235443	Non-volatile memory and method of manufacturing floating gate A method of manufacturing a floating gate is provided. The method includes the steps of forming a tunneling layer on a substrate, and forming a film layer containing a semiconductor component on the tunneling layer. The film layer consists of a semiconductor film or...	06/26/2007
7232772	Substrate processing method A substrate processing method comprises the step of forming an oxide film on a silicon substrate surface, and introducing nitrogen atoms into the oxide film by exposing the oxide film to nitrogen radicals excited in plasma formed by a microwave introduced via a plan...	06/19/2007
7229867	Process for producing a field-effect transistor and transistor thus obtained A substrate supporting a portion of a semiconductor material is used to produce a field-effect transistor. A portion of a temporary material lies between the portion of semiconductor material and the substrate. A gate is formed, which comprises an upper part in rigi...	06/12/2007
7220684	Semiconductor device and method of manufacturing the same There is included an inorganic insulating film having a porous structure including a cylindrical vacancy oriented in parallel with the surface of a substrate subjected to a hydrophilic treatment or a hydrophobic treatment. ...	05/22/2007
7220641	Method for fabricating storage electrode of semiconductor device The present invention discloses improved method for manufacturing semiconductor device wherein a barrier layer is formed by thermally treating a hard mask polysilicon layer for protecting the sacrificial oxide film and the hard mask polysilicon film from damages.	05/22/2007
7195983	Programming, erasing, and reading structure for an NVM cell A non-volatile memory (NVM) has a silicon germanium (SiGe) drain and a silicon carbon (SiC) source. The source being SiC provides for a stress on the channel that improves N channel mobility. The SiC also has a larger bandgap than the substrate, which is silicon. Th...	03/27/2007
7183162	Method of forming non-volatile memory cell using sacrificial pillar spacers and non-volatile memory cell formed according to the method A method of forming a microelectronic non-volatile memory cell, a memory cell formed according to the method, and a system including the memory cell. The method comprises: providing a substrate; providing a pair of spaced apart isolation bodies on the substrate, the...	02/27/2007

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Class 257/E21.209 - Making electrode structure comprising conductor-insulator-conuctor-insulator-semiconductor, e.g., gate stack for non-volatile memory (EPO)