Class 257/E21.206 - Lithography, isolation, or planarization-related aspects of making conductor-insulator-semiconductor structure, e.g., sub-lithography lengths; to solve problems arising at crossing with side of device isolation (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.195. This subclass
No. of patents: 373
Last issue date: 10/21/2008

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Number	Title	Issue Date
7439602	Semiconductor device and its manufacturing method A semiconductor device including memory cells isolated by a trench that may be self aligned with a stacked film pattern (7) has been disclosed. The memory cells may be flash memory cells having an active gate film (2) that may be thinner than a gate ox...	10/21/2008
7425496	Method for delineating a conducting element disposed on an insulating layer, device and transistor thus obtained A conducting layer is deposited on an insulating layer disposed on a substrate. A mask is formed on at least one area of the conducting layer, thus delineating in the conducting layer at least one complementary area not covered by the mask. The complementary areas o...	09/16/2008
7425489	Self-aligned shallow trench isolation A method of making a semiconductor structure includes etching an isolation oxide. The isolation oxide is in a substrate, a gate layer is on the substrate, a patterned metallic layer is on the gate layer, and a first patterned etch-stop layer is on the metallic layer...	09/16/2008
7399649	Semiconductor light-emitting device and fabrication method thereof An underlying layer ALY of GaN is formed on a sapphire substrate SSB; a transfer layer TLY of GaN with a bump and dip shaped surface is formed on the underlying layer ALY; a light absorption layer BLY is formed on the bump and dip shaped surface of the transfer laye...	07/15/2008
7393789	Protective coating for planarization Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolida...	07/01/2008
7394120	Semiconductor device having a shaped gate electrode and method of manufacturing the same An MIS transistor includes a gate electrode located to intersect a device region of a semiconductor substrate isolated by a device isolation region, and source and drain regions formed in the semiconductor substrate at both sides of the gate electrode region and ele...	07/01/2008
7386182	Optimization of multiple feature lithography According to one embodiment of the invention, a method for enhancing multiple feature lithography is provided. The method includes generating a plurality of maps each associated with a particular one of a plurality of circuit features. Each map maps an illumination ...	06/10/2008
7355239	Fabrication of semiconductor device exhibiting reduced dielectric loss in isolation trenches Improved methods of manufacturing semiconductor devices are provided to reduce dielectric loss in isolation trenches of the devices. In one example, a method of manufacturing a semiconductor device includes forming a plurality of shallow trench isolation (STI) trenc...	04/08/2008
7332405	Method of forming alignment marks for semiconductor device fabrication A semiconductor integrated circuit is fabricated in a substrate having a semiconductor layer and an underlying insulator layer. The fabrication process includes a step of locally oxidizing the semiconductor layer to form a field oxide, during which step the semicond...	02/19/2008
7316958	Masks for fabricating semiconductor devices and methods of forming mask patterns Masks for fabricating a semiconductor device and methods of forming mask patterns are provided which are capable of enhancing the breakdown voltage of the fabricated semiconductor device by accurately correcting a line width pattern error of a semiconductor substrat...	01/08/2008
7296245	Combined e-beam and optical exposure semiconductor lithography Combined e-beam and optical exposure lithography for semiconductor fabrication is disclosed. E-beam direct writing to is employed to create critical dimension (CD) areas of a semiconductor design on a semiconductor wafer. Optical exposure lithography is employed to ...	11/13/2007
7291554	Method for forming semiconductor device A method for forming a semiconductor device includes the steps of forming a flowable film made of an insulating material with flowability; forming a first concave portion in the flowable film through transfer of a convex portion of a pressing face of a pressing memb...	11/06/2007
7265013	Sidewall image transfer (SIT) technologies A structure fabrication method. The method comprises providing a structure which comprises (a) a to-be-etched layer, (b) a memory region, (c) a positioning region, (d) and a capping region on top of one another. Then, the positioning region is indented. Then, a conf...	09/04/2007
7253105	Reliable BEOL integration process with direct CMP of porous SiCOH dielectric The present invention relates to methods of improving the fabrication of interconnect structures of the single or dual damascene type, in which there is no problem of hard mask retention or of conductivity between the metal lines after fabrication. The methods of th...	08/07/2007
7247571	Method for planarizing semiconductor structures A method for planarizing a semiconductor structure is disclosed. A semiconductor substrate having a first area in which one or more trenches are formed in a first pattern density, and a second area in which one or more trenches are formed in a second pattern density...	07/24/2007
7163879	Hard mask etch for gate polyetch A transistor gate structure that is free from notches is formed by using a hard mask. The hard mask has a bilayer structure of a BARC (bottom antireflective coating) over a silicon dioxide layer. A photoresist layer is formed over a portion corresponding to the gate...	01/16/2007
7153781	Method to etch poly Si gate stacks with raised STI structure In a process for etching poly Si gate stacks with raised STI structure where the thickness of poly Si gates at the AA and STI are different, the improvement comprising: a) etching a gate silicide layer+a poly Si 2 layer; ...	12/26/2006
7087532	Formation of controlled sublithographic structures A process for forming sublithographic structures such as fins employs a hardmask protective layer above a hardmask to absorb damage during a dry etching step, thereby preserving symmetry in the hardmask and eliminating a source of defects. ...	08/08/2006
7020859	Process skew results for integrated circuits A method of performing a characterization of an integrated circuit design that is customized during succeeding fabrication steps. The characterization is accomplished with respect to different levels of a processing parameter that is fixed during preceding fabricati...	03/28/2006
6703672	Polysilicon/amorphous silicon composite gate electrode A polysilicon/amorphous silicon composite layer for improved linewidth control in the patterning of gate electrodes, in the manufacture of metal oxide semiconductor (MOS) devices. The formation of a composite polysilicon/amorphous silicon gate in an integ...	03/09/2004
6696743	Semiconductor transistor having gate electrode and/or gate wiring A semiconductor transistor formed between trench device isolation regions comprises; a gate electrode formed on a device formation region with the intervention of a gate insulating film and extended over the trench device isolation regions, a distance fro...	02/24/2004
6693341	Semiconductor device When an element isolation film is formed by the LOCOS technique, as an underlying buffer layer of an oxidation resisting film, a pad oxidation film and pad poly-Si film are used. When an element is formed, they are used as a gate oxide film and a part of ...	02/17/2004
6677211	Method for eliminating polysilicon residue A method for eliminating polysilicon residue is provided by converting the polysilicon residue into silicon nitride in two steps. A tilted ion implantation step is performed to implant nitrogen ions into the polysilicon residue to rich nitrogen containing...	01/13/2004
6677661	Semiconductive wafer assemblies In one aspect, the invention includes a semiconductor fabrication process, comprising: a) providing a substrate; b) forming a layer of silicon nitride over the substrate, the layer having a thickness; and c) enriching a portion of the thickness of the sil...	01/13/2004
6673685	Method of manufacturing semiconductor devices A process for economical and efficient fabrication of gate electrodes no larger than 50 nm, which is beyond the limit of exposure, is characterized by gate-electrode trimming and mask trimming with high resist selectivity which are performed in combinatio...	01/06/2004
6670288	Methods of forming a layer of silicon nitride in a semiconductor fabrication process In one aspect, the invention includes a semiconductor fabrication process, comprising: a) providing a substrate; b) forming a layer of silicon nitride over the substrate, the layer having a thickness; and c) enriching a portion of the thickness of the sil...	12/30/2003
6670277	Method of manufacturing semiconductor device A semiconductor device manufacturing method for manufacturing a semiconductor device of constant finished dimensions as designed even when a material which is difficult to increase etch selectivity to a silicon film in a gate electrode or wiring structure...	12/30/2003
6664592	Semiconductor device with groove type channel structure A semiconductor device includes a semiconductor substrate, a gate insulator film formed on a bottom surface and a side surface of a groove formed in the semiconductor substrate, a gate electrode having a lower portion buried in the groove on whose bottom ...	12/16/2003
6656796	Multiple etch method for fabricating split gate field effect transistor (FET) device Within a method for fabricating a split gate field effect transistor (FET) device there is employed a two step etch method for forming a floating gate electrode. Within the two step etch method there is employed a patterned first masking layer and a blank...	12/02/2003
6651678	Method of manufacturing semiconductor device A method of etching a semiconductor device preventing tapering of a gate electrode edge includes a main etching of an electrode or wiring material supported by a dielectric film at a semiconductor substrate surface to expose the dielectric film. After the...	11/25/2003
6653225	Method for forming gate electrode structure with improved profile and gate electrode structure therefor A gate electrode, in which the slope of the profile of a gate electrode forming material layer, for example, a refractory metal silicide layer is prevented from being decreased due to thermal expansion by patterning a refractory metal silicide layer after...	11/25/2003
6653231	Process for reducing the critical dimensions of integrated circuit device features A process for forming sub-lithographic features in an integrated circuit is disclosed herein. A process for enhancing the etch trimmability and the etch stability of features patterned on a photoresist layer is also disclosed herein. The process includes ...	11/25/2003
6649308	Ultra-short channel NMOSFETS with self-aligned silicide contact The ultra-short channel transistor in a semiconductor substrate includes a gate structure that is formed on the substrate. Side-wall spacers are formed on the side walls of the gate structure as an impurities-diffusive source. Source and drain regions are...	11/18/2003
6645840	Multi-layered polysilicon process A method for forming a notched MOS gate structure is described. A multi-layer gate structure is formed (150) where the top layer (140) oxidizes at a faster rate compared to the bottom layer (130). This results in the formation of a notch (165) in the gate...	11/11/2003
6635584	Versatile system for forming uniform wafer surfaces A system for fabricating an integrated circuit is disclosed that includes providing a semiconductor substrate (10), and forming a gate oxide layer (12) on an active area on the substrate. A polysilicon gate (14) is formed, on top of the gate oxide, by etc...	10/21/2003
6633072	Fabrication method for semiconductor integrated circuit devices and semiconductor integrated circuit device To improve the shape of a gate electrode having SiGe, after patterning a gate electrode 15G having an SiGe layer 15b by a dry etching process, a plasma processing (postprocessing) is carried out in an atmosphere of an Ar/CHF3 gas. Thereby, the ...	10/14/2003
6630288	Process for forming sub-lithographic photoresist features by modification of the photoresist surface A process for forming sub-lithographic features in an integrated circuit is disclosed herein. The process includes modifying a photoresist layer after patterning and development but before it is utilized to pattern the underlying layers. The modified phot...	10/07/2003
6630405	Method of gate patterning for sub-0.1 μm technology A method of gate patterning, including the following steps. A semiconductor structure having an upper silicon layer is provided. The semiconductor structure has a gate conductor region. A first gate oxide layer is formed over the semiconductor structure. ...	10/07/2003
6627557	Semiconductor device and method for manufacturing the same Disclosed is a method of manufacturing a semiconductor device, which comprises the steps of forming an insulating film or a metal film on a surface of a semiconductor substrate, forming at least two kinds of mask on a surface of the insulating film or the...	09/30/2003
6627360	Carbonization process for an etch mask A method of forming an etch mask includes patterning a top surface of a photoresist layer, carbonizing the patterned top surface of the photoresist layer and selectively removing portions of the photoresist layer. Portions of the photoresist layer under t...	09/30/2003

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Class 257/E21.206 - Lithography, isolation, or planarization-related aspects of making conductor-insulator-semiconductor structure, e.g., sub-lithography lengths; to solve problems arising at crossing with side of device isolation (EPO)