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| Number | Title | Issue Date |
| 7439166 | Method for producing tiered gate structure devices In one implementation, a method for fabricating a tiered structure is provided, which includes forming a source and a drain on a substrate with a gate formed therebetween. Formation of the gate includes depositing a gate foot using a gate foot mask having an opening... | 10/21/2008 |
| 7432120 | Method for realizing a hosting structure of nanometric elements Method for manufacturing a hosting structure of nanometric elements comprising the steps of depositing on an upper surface of a substrate, of a first material, a block-seed having at least one side wall. Depositing on at least one portion of sad surface and on the b... | 10/07/2008 |
| 7432564 | Pixel structure A method for fabricating a pixel structure is provided. First, a gate, a scan line, and a first terminal are formed on a substrate. A gate insulating layer is formed over the substrate to cover the gate, the scan line, and the first terminal. After defining the semi... | 10/07/2008 |
| 7387955 | Field effect transistor and method for manufacturing the same A field effect transistor having a T- or Γ-shaped fine gate electrode of which a head portion is wider than a foot portion, and a method for manufacturing the field effect transistor, are provided. A void is formed between the head portion of the gate electrode and... | 06/17/2008 |
| 7384852 | Sub-lithographic gate length transistor using self-assembling polymers A semiconductor structure including at least one transistor located on a surface of a semiconductor substrate, wherein the at least one transistor has a sub-lithographic channel length, is provided. Also provided is a method to form such a semiconductor structure us... | 06/10/2008 |
| 7374989 | Flash memory and methods of fabricating the same Flash memory and methods of fabricating the same are disclosed. An illustrated example flash memory includes a first source formed within a semiconductor substrate; an epitaxial layer formed on an upper surface of the semiconductor substrate; an opening formed withi... | 05/20/2008 |
| 7354821 | Methods of fabricating trench capacitors with insulating layer collars in undercut regions Trench capacitors that have insulating layer collars in undercut regions and methods of fabricating such trench capacitors are provided. Some methods of fabricating a trench capacitor include forming a first layer on a substrate. A second layer is formed on the firs... | 04/08/2008 |
| 7341920 | Method for forming a bipolar transistor device with self-aligned raised extrinsic base Disclosed are embodiments of a method of fabricating a bipolar transistor with a self-aligned raised extrinsic base. In the method a dielectric pad is formed on a substrate with a minimum dimension capable of being produced using current state-of-the-art lithographi... | 03/11/2008 |
| 7335542 | Semiconductor device with mushroom electrode and manufacture method thereof A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed ... | 02/26/2008 |
| 7326621 | Method of fabricating a recess channel array transistor using a mask layer with a high etch selectivity with respect to a silicon substrate A method of fabricating a recess channel array transistor. Using a mask layer pattern having a high etch selectivity with respect to a silicon substrate, the silicon substrate and an isolation insulating layer are etched to form a recess channel trench. After formin... | 02/05/2008 |
| 7282423 | Method of forming fet with T-shaped gate An FET has a T-shaped gate. The FET has a halo diffusion self-aligned to the bottom portion of the T and an extension diffusion self aligned to the top portion. The halo is thereby separated from the extension implant, and this provides significant advantages. The t... | 10/16/2007 |
| 7223645 | Semiconductor device with mushroom electrode and manufacture method thereof A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed ... | 05/29/2007 |
| 7198996 | Component built-in module and method for producing the same A component built-in module including a core layer formed of an electric insulating material, and an electric insulating layer and a plurality of wiring patterns, which are formed on at least one surface of the core layer. The electric insulating material of the cor... | 04/03/2007 |
| 7186607 | Charge-trapping memory device and method for production A thin SiGe layer is provided as an additional lower gate electrode layer and is arranged between a thin gate oxide and a gate electrode layer, preferably of polysilicon. The SiGe layer can be etched selectively to the gate electrode and the gate oxide and is latera... | 03/06/2007 |
| 7176534 | Low resistance T-gate MOSFET device using a damascene gate process and an innovative oxide removal etch The present invention provides a method for fabricating low-resistance, sub-0.1 μm channel T-gate MOSFETs that do not exhibit any poly depletion problems. The inventive method employs a damascene-gate processing step and a chemical oxide removal etch to fabricate s... | 02/13/2007 |
| 7129564 | Structure and method of forming a notched gate field effect transistor The structure and method of forming a notched gate MOSFET disclosed herein addresses such problems as device reliability. A gate dielectric (e.g. gate oxide) is formed on the surface of an active area on the semiconductor substrate, preferably defined by an isolatio... | 10/31/2006 |
| 7101766 | Methods of fabricating semiconductor device having T-shaped gate and L-shaped spacer There are provided methods of fabricating a semiconductor device having a T-shaped gate and an L-shaped spacer. In the method, an insulating layer and a sacrificial layer are formed in sequence on a semiconductor substrate having a vertical gate pattern. By etching ... | 09/05/2006 |
| 7087499 | Integrated antifuse structure for FINFET and CMOS devices A method is described for fabricating and antifuse structure (100) integrated with a semiconductor device such as a FINFET or planar CMOS devise. A region of semiconducting material (11) is provided overlying an insulator (3) disposed on a subst... | 08/08/2006 |
| 6894357 | Gate stack for high performance sub-micron CMOS devices A new method is provided for the creation of sub-micron gate electrode structures. A high-k dielectric is used for the gate dielectric, providing increased inversion carrier density without having to resort to aggressive scaling of the thickness of the gate dielectr... | 05/17/2005 |
| 6703271 | Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer A process for fabricating CMOS devices, featuring a channel region comprised with a strained SiGe layer, has been developed. The process features the selective growth of a composite silicon layer on the top surface of N well and P well regions. The compos... | 03/09/2004 |
| 6699755 | Method for producing a gate A method for producing a gate on a semiconductor substrate. The semiconductor substratehas a first oxide layer, a conductive layer, a silicide layer, and a hard mask formed thereon. The method includes defining the hard mask to form a pattern of the gate,... | 03/02/2004 |
| 6693313 | Field effect transistors, field effect transistor assemblies, and integrated circuitry The invention encompasses integrated circuitry which includes a semiconductive material substrate and a first field effect transistor supported by the substrate. The first field effect transistor comprises a first transistor gate assembly which includes a... | 02/17/2004 |
| 6674139 | Inverse T-gate structure using damascene processing A field effect transistor has an inverse-T gate conductor having a thicker center portion and thinner wings. The wings may be of a different material different than the center portion. In addition, gate dielectric may be thicker along edges than in the ce... | 01/06/2004 |
| 6664592 | Semiconductor device with groove type channel structure A semiconductor device includes a semiconductor substrate, a gate insulator film formed on a bottom surface and a side surface of a groove formed in the semiconductor substrate, a gate electrode having a lower portion buried in the groove on whose bottom ... | 12/16/2003 |
| 6661066 | Semiconductor device including inversely tapered gate electrode and manufacturing method thereof A semiconductor device and manufacturing method including a MOSFET having a trench-type element isolation structure (2) formed on a main surface of a semiconductor substrate (1). A pair of extensions (3) and source/drain regions (4) are selectively formed... | 12/09/2003 |
| 6656824 | Low resistance T-gate MOSFET device using a damascene gate process and an innovative oxide removal etch The present invention provides a method for fabricating low-resistance, sub-0.1 μm channel T-gate MOSFETs that do not exhibit any poly depletion problems. The inventive method employs a damascene-gate processing step and a chemical oxide removal etch to ... | 12/02/2003 |
| 6656808 | Transistor having variable width gate electrode and method of manufacturing the same A transistor includes a substrate and a gate electrode formed on the substrate and having a wider upper portion than lower portion. A spacer is formed on the side wall of the gate electrode from the upper portion to the lower portion of the gate electrode... | 12/02/2003 |
| 6649462 | Semiconductor device and method of manufacturing the same including T-shaped gate A gate insulating film is provided on a channel region. A gate electrode includes a lower part and an upper part. The lower part has a lower surface and sides, and the upper part has a lower surface. The lower surface of the lower part contacts the gate i... | 11/18/2003 |
| 6649460 | Fabricating a substantially self-aligned MOSFET The present invention includes methods and structures for forming at least a substantially self-aligned MOSFET. According to the present invention, a method of fabricating a semiconductor device includes providing a substrate; providing first materials (s... | 11/18/2003 |
| 6646326 | Method and system for providing source/drain-gate spatial overlap engineering for low-power devices A method and system for providing a semiconductor device on a substrate are disclosed. The method and system include providing a tunneling barrier on the substrate and providing at least one gate on the tunneling barrier. The at least one of gate includes... | 11/11/2003 |
| 6645840 | Multi-layered polysilicon process A method for forming a notched MOS gate structure is described. A multi-layer gate structure is formed (150) where the top layer (140) oxidizes at a faster rate compared to the bottom layer (130). This results in the formation of a notch (165) in the gate... | 11/11/2003 |
| 6645821 | Method of producing a thin film resistor in an integrated circuit A thin film resistor (60) is contained between two metal interconnect layers (40, 100) of an integrated circuit. Contact may be made to the resistor (60) through vias (95) from the metal layer (100) above the resistor (60) to both the thin film resistor (... | 11/11/2003 |
| 6638801 | Semiconductor device and its manufacturing method A semiconductor device including an IGFET (insulated gate field effect transistor) (30) is disclosed. IGFET (30) may include a source/drain area (15) having an impurity concentration distribution that may be formed shallower at a higher concentration than... | 10/28/2003 |
| 6633070 | Semiconductor device A field-effect transistor including a gate electrode, silicon layers, and source and drain regions at a surface of a silicon substrate. Sidewall insulating films on the opposite side surfaces of the gate electrode are located between the gate electrode an... | 10/14/2003 |
| 6632717 | Transistor of semiconductor device and method of manufacturing the same The present invention relates to a transistor of a semiconductor and a method of fabricating the same. In the method, the dual gate electrode may have different widths and is formed using a damascene process. The dual gate electrode is formed using a stac... | 10/14/2003 |
| 6630712 | Transistor with dynamic source/drain extensions A method of fabricating an integrated circuit with a transistor having less susceptibility to off-state leakage current and short-channel effect is disclosed. The transistor includes high-K gate dielectric spacers and a T-shaped gate conductor. The high-K... | 10/07/2003 |
| 6627558 | Apparatus and method for selectively restricting process fluid flow in semiconductor processing A semiconductor processing apparatus (10) is disclosed which includes a process chamber (12) and at least one substrate support (18) disposed within the process chamber (12) operable to support a substrate wafer (20). The semiconductor processing apparatu... | 09/30/2003 |
| 6624483 | Semiconductor device having an insulated gate and a fabrication process thereof A semiconductor device includes a T-shaped gate on a gate insulation film, wherein the T-shaped gate includes a lower polycrystal layer containing Si and Ge and an upper polycrystal layer of polysilicon.... | 09/23/2003 |
| 6624057 | Method for making an access transistor Methods are disclosed for the fabrication of novel polysilicon structures having increased surface areas to achieve lower resistances after silicidation. The structures are applicable, for example, to semiconductor interconnects, polysilicon gate, and cap... | 09/23/2003 |
| 6624486 | Method for low topography semiconductor device formation A method for forming a planarized field effect transistor (FET) is disclosed. In an exemplary embodiment of the invention, the method includes defining an active semiconductor region upon a substrate, the active semiconductor region further comprising a p... | 09/23/2003 |
