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| Number | Title | Issue Date |
| 7419905 | Gate electrodes and the formation thereof A method of fabricating a gate electrode for a semiconductor comprising the steps of: providing a substrate; providing on the substrate a layer of a first material of thickness tp, the first material being selected from the group consisting of Si, Si... | 09/02/2008 |
| 7419907 | Eliminating metal-rich silicides using an amorphous Ni alloy silicide structure The present invention provides a method for producing thin nickel (Ni) monosilicide or NiSi films (having a thickness on the order of about 30 nm or less), as contacts in CMOS devices wherein an amorphous Ni alloy silicide layer is formed during annealing which elim... | 09/02/2008 |
| 7399669 | Semiconductor devices and methods for fabricating the same including forming an amorphous region in an interface between a device isolation layer and a source/drain diffusion layer Semiconductor devices and methods for fabricating the same are disclosed in which an amorphous layer is formed in an interface between a device isolation layer and a source or drain region to stably thin a silicide layer formed in the interface. A leakage current of... | 07/15/2008 |
| 7396716 | Method to obtain fully silicided poly gate The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises forming a capping layer 610 over gate structures 230 located over a microelectronics substrate 210 wherein the gate structures ... | 07/08/2008 |
| 7361597 | Semiconductor device and method of fabricating the same A semiconductor device incorporating an alloy layer formed on a substrate; a gate electrode, a source electrode, and a drain electrode formed on the alloy layer at predetermined intervals therebetween; a gate insulating layer formed on the gate electrode in a gate e... | 04/22/2008 |
| 7351659 | Methods of forming a transistor with an integrated metal silicide gate electrode Methods of forming a transistor having integrated metal silicide transistor gate electrode on a semiconductor assembly are described. The transistor gate is partially fabricated by reacting the metal with epitaxial silicon while residing in a trench to form metal si... | 04/01/2008 |
| 7329599 | Method for fabricating a semiconductor device Methods are provided for semiconductor devices having low contact resistance. The method in accordance with one embodiment of the invention comprises forming an insulating layer overlying a semiconductor substrate, the semiconductor substrate having a device region ... | 02/12/2008 |
| 7326644 | Semiconductor device and method of fabricating the same A method of fabricating a semiconductor device, includes (a) forming an oxide film entirely over a silicon substrate on which a MOS transistor is fabricated, (b) carrying out first thermal-annealing to the silicon substrate, (c) removing the oxide film in an area wh... | 02/05/2008 |
| 7314830 | Method of fabricating semiconductor integrated circuit device with 99.99 wt% cobalt A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target ha... | 01/01/2008 |
| 7306998 | Formation of abrupt junctions in devices by using silicide growth dopant snowplow effect A method of forming an abrupt junction device with a semiconductor substrate is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed on the gate dielectric. A sidewall spacer is formed on the semiconductor substrate adjacent the g... | 12/11/2007 |
| 7256123 | Method of forming an interface for a semiconductor device In a semiconductor device using a polysilicon contact, such as a poly plug between a transistor and a capacitor in a container cell, an interface is provided where the poly plug would otherwise contact the bottom plate of the capacitor. The interface bars silicon fr... | 08/14/2007 |
| 7253472 | Method of fabricating semiconductor device employing selectivity poly deposition A method for fabricating a semiconductor device employing a selectivity poly deposition is disclosed. The disclosed method comprises depositing selectivity poly on a gate poly and source/drain regions of the silicon substrate, and forming salicide regions on the gat... | 08/07/2007 |
| 7244996 | Structure of a field effect transistor having metallic silicide and manufacturing method thereof A field effect transistor having metallic silicide layers is formed in a semiconductor layer on an insulating layer of an SOI substrate. The metallic silicide layers are composed of refractory metal and silicon. The metallic silicide layers extend to bottom surfaces... | 07/17/2007 |
| 7238612 | Methods of forming a double metal salicide layer and methods of fabricating semiconductor devices incorporating the same A metal salicide layer is formed by sequentially depositing a physical vapor deposition (PVD) metal layer and a chemical vapor deposition (CVD) metal layer on a semiconductor device having an exposed silicon surface so as to form a double metal layer. The semiconduc... | 07/03/2007 |
| 7232756 | Nickel salicide process with reduced dopant deactivation Provided are exemplary methods for forming a semiconductor devices incorporating silicide layers formed at temperatures below about 700° C., such as nickel silicides, that are formed after completion of a silicide blocking layer (SBL). The formation of the SBL tend... | 06/19/2007 |
| 7226827 | Method for fabricating semiconductor devices having silicided electrodes The invention relates to a method for fabricating a semiconductor device having a semiconductor body that comprises a first semiconductor structure having a dielectric layer and a first conductor, and a second semiconductor structure having a dielectric layer and a ... | 06/05/2007 |
| 7214577 | Method of fabricating semiconductor integrated circuit device A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETs by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target ha... | 05/08/2007 |
| 7208414 | Method for enhanced uni-directional diffusion of metal and subsequent silicide formation The present invention provides a method for enhancing uni-directional diffusion of a metal during silicidation by using a metal-containing silicon alloy in conjunction with a first anneal in which two distinct thermal cycles are performed. The first thermal cycle of... | 04/24/2007 |
| 7208398 | Metal-halogen physical vapor deposition for semiconductor device defect reduction The present invention provides a method of manufacturing a metal silicide electrode (100) for a semiconductor device (110). The method comprises depositing by physical vapor deposition, halogen atoms (120) and transition metal atoms (130)... | 04/24/2007 |
| 7179714 | Method of fabricating MOS transistor having fully silicided gate There is provided a method of fabricating a MOS transistor having a fully silicided gate, including forming a gate pattern and gate spacers on a semiconductor substrate, the gate pattern including a lower gate pattern, an insulating layer pattern, and an upper gate ... | 02/20/2007 |
| 7172967 | Methods for forming cobalt layers including introducing vaporized cobalt precursors and methods for manufacturing semiconductor devices using the same The present invention provides methods for forming cobalt silicide layers, including introducing a vaporized cobalt precursor onto a silicon substrate to form a cobalt layer. The vaporized cobalt precursor has the formula Co2(CO)6(R1... | 02/06/2007 |
| 7105429 | Method of inhibiting metal silicide encroachment in a transistor A method inhibits metal silicide encroachment in channel regions in a transistor that uses metal silicide as an electrical contact to its terminals. A metal layer is deposited overlying the transistor. A first anneal that is a low temperature anneal forms metal sili... | 09/12/2006 |
| 6693341 | Semiconductor device When an element isolation film is formed by the LOCOS technique, as an underlying buffer layer of an oxidation resisting film, a pad oxidation film and pad poly-Si film are used. When an element is formed, they are used as a gate oxide film and a part of ... | 02/17/2004 |
| 6689685 | Process for forming a diffusion barrier material nitride film A process is disclosed for manufacturing a film that is smooth and has large nitride grains of a diffusion barrier material. Under the process, a nitride of the diffusion barrier material is deposited by physical vapor deposition in an environment of nitr... | 02/10/2004 |
| 6680246 | Process for forming a nitride film A process is disclosed for manufacturing a film that is smooth and has large nitride grains of a diffusion barrier material. Under the process, a nitride of the diffusion barrier material is deposited by physical vapor deposition in an environment of nitr... | 01/20/2004 |
| 6673665 | Semiconductor device having increased metal silicide portions and method of forming the semiconductor The surface area of silicon lines which receives a silicide portion is increased to decrease the line resistance in narrow polysilicon lines, such as gate electrodes. Sidewall spacers are formed such that an upper portion of the line sidewall is exposed s... | 01/06/2004 |
| 6657265 | Semiconductor device and its manufacturing method A semiconductor device includes metal silicide films formed on the surface of a source-drain region and of a gate electrode. On the metal silicide films, impurity regions are formed of a conductivity type opposite to the conductivity type of the source-dr... | 12/02/2003 |
| 6653225 | Method for forming gate electrode structure with improved profile and gate electrode structure therefor A gate electrode, in which the slope of the profile of a gate electrode forming material layer, for example, a refractory metal silicide layer is prevented from being decreased due to thermal expansion by patterning a refractory metal silicide layer after... | 11/25/2003 |
| 6642592 | Semiconductor device and method for fabricating same A semiconductor device and method for fabricating the same which improves reliability of the semiconductor device is disclosed. The semiconductor device includes: a first insulating film and a gate electrode sequentially formed on a part of a semiconducto... | 11/04/2003 |
| 6638843 | Method for forming a silicide gate stack for use in a self-aligned contact etch A method for forming a gate stack having a silicide layer that can subsequently undergo a SAC etch is disclosed. The present method provides a layer of insulating material on top of the silicide layer. The insulating material is sufficient to protect the ... | 10/28/2003 |
| 6635556 | Method of preventing autodoping A method of making a silicon-based electronic device is provided. The method includes, for example, the steps of forming a doped silicon layer on a surface of a substrate material and forming an undoped silicon capping layer on the doped silicon layer. Th... | 10/21/2003 |
| 6630721 | Polysilicon sidewall with silicide formation to produce high performance MOSFETS A MOSFET transistor having silicide formed on top of a polysilicon gate conductor, on partially exposed sidewalls of the polysilicon gate conductor, and on junction regions in an underlying semiconductor substrate is provided. Opposed sidewalls of the pol... | 10/07/2003 |
| 6627526 | Method for fabricating a conductive structure for a semiconductor device A process for making semiconductor structures, and the resulting highly conductive semiconductor structures, includes using damascene process to form a structure with a thin adhesive layer and overlaying conductive layer. The highly conductive semiconduct... | 09/30/2003 |
| 6627527 | Method to reduce metal silicide void formation A method of forming a low resistance metal silicide layer on a narrow width, conductive gate structure, has been developed. After formation of a metal silicide layer on a conductive gate structure via a self-aligned metal silicide (salicide), procedure, u... | 09/30/2003 |
| 6624489 | Formation of silicided shallow junctions using implant through metal technology and laser annealing process A method for producing MOS type transistors with deep source/drain junctions and thin, silicided contacts with desireable interfacial and electrical properties. The devices are produced by a method that involves pre-amorphization of the gate, source and d... | 09/23/2003 |
| 6620703 | Method of forming an integrated circuit using an isolation trench having a cavity formed by reflowing a doped glass mask layer Isolation characteristics of an isolation trench can be enhanced. Elements to be isolated by an isolation trench (STI 2) are formed in active semiconductor regions shown by arrows 30 and 31 on a semiconductor substrate 1. The STI 2 is filled with SiOF.... | 09/16/2003 |
| 6613673 | Technique for elimination of pitting on silicon substrate during gate stack etch A method for forming a gate stack which minimizes or eliminates damage to the gate dielectric layer and/or silicon substrate during the gate stack formation by the reduction of the temperature during formation. The temperature reduction prevents the forma... | 09/02/2003 |
| 6593633 | Method and device for improved salicide resistance on polysilicon gates The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Anothe... | 07/15/2003 |
| 6586331 | Low sheet resistance of titanium salicide process A method for establishing low sheet resistance for the Titanium Salicide process that teaches a C-54 TiSix process by means of an additional vacuum bake. The present invention teaches an additional vacuum bake step prior to pre-metal HF dip dur... | 07/01/2003 |
| 6586809 | Semiconductor device and method for fabricating the same A gate insulating film, a gate electrode, a gate-top protection film, LDD layers and nitride film sidewalls are formed on a semiconductor substrate. Source/drain regions are formed in the semiconductor substrate. After deposition of an interlayer insulati... | 07/01/2003 |
