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| Number | Title | Issue Date |
| 7365027 | ALD of amorphous lanthanide doped TiOfilms The use of atomic layer deposition (ALD) to form an amorphous dielectric layer of titanium oxide (TiOx) doped with lanthanide elements, such as samarium, europium, gadolinium, holmium, erbium and thulium, produces a reliable structure for use in a variety... | 04/29/2008 |
| 7224026 | Nanoelectronic devices and circuits Diode devices with superior and pre-settable characteristics and of nanometric dimensions, comprise etched insulative lines (8, 16, 18) in a conductive substrate to define between the lines charge carrier flow paths, formed as elongate channels (20) at... | 05/29/2007 |
| 6703672 | Polysilicon/amorphous silicon composite gate electrode A polysilicon/amorphous silicon composite layer for improved linewidth control in the patterning of gate electrodes, in the manufacture of metal oxide semiconductor (MOS) devices. The formation of a composite polysilicon/amorphous silicon gate in an integ... | 03/09/2004 |
| 6682994 | Methods for transistor gate formation using gate sidewall implantation Methods are disclosed for semiconductor device fabrication in which MOS transistor gates are to be formed. Polysilicon gate structures and sidewall spacers are formed, with upper portions of the gate sidewalls exposed. Angled implantation processing is em... | 01/27/2004 |
| 6670263 | Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting structure may have two or mo... | 12/30/2003 |
| 6664153 | Method to fabricate a single gate with dual work-functions A method for forming a single gate having a dual work-function is described. A gate electrode is formed overlying a gate dielectric layer on a substrate. Sidewalls of the gate electrode are selectively doped whereby the doped sidewalls have a first work-f... | 12/16/2003 |
| 6660608 | Method for manufacturing CMOS device having low gate resistivity using aluminum implant A CMOS device (10) having p-channel and n-channel transistors with aluminum implanted gates (20). When making the device (10), aluminum is non-selectively implanted to form a source and drain for the n-channel transistor and to reduce the resistivity of t... | 12/09/2003 |
| 6653699 | Polysilicon/Amorphous silicon gate structures for integrated circuit field effect transistors Gate electrodes for integrated circuit field effect transistors are fabricated by forming a polysilicon layer on a gate insulating layer opposite an integrated circuit substrate, forming an amorphous impurity layer on the polysilicon layer opposite the ga... | 11/25/2003 |
| 6645840 | Multi-layered polysilicon process A method for forming a notched MOS gate structure is described. A multi-layer gate structure is formed (150) where the top layer (140) oxidizes at a faster rate compared to the bottom layer (130). This results in the formation of a notch (165) in the gate... | 11/11/2003 |
| 6627971 | Polysilicon structures with different resistance values for gate electrodes, resistors, and capacitor plates A device with a plurality of structures with different resistance values is formed on a substrate. A polysilicon layer is formed upon the substrate. A silicon oxide layer is formed over the substrate. A hard masking layer is formed over the silicon oxide ... | 09/30/2003 |
| 6620671 | Method of fabricating transistor having a single crystalline gate conductor A method of manufacturing an integrated circuit on a substrate provides a gate structure including single crystalline material. The method can provide a first amorphous or polycrystalline semiconductor layer above a top surface of the substrate and patter... | 09/16/2003 |
| 6620713 | Interfacial layer for gate electrode and high-k dielectric layer and methods of fabrication Method of fabricating a semiconductor device. The semiconductor device comprises a substrate, a high-k gate dielectric layer formed on the substrate, and a hydrogen-free gate electrode deposited on the high-k gate dielectric layer wherein the hydrogen-fre... | 09/16/2003 |
| 6613695 | Surface preparation prior to deposition Methods are provided herein for treating substrate surfaces in preparation for subsequent nucleation-sensitive depositions (e.g., polysilicon or poly-SiGe) and adsorption-driven deposition (e.g. atomic layer deposition or ALD). Prior to depositing, the su... | 09/02/2003 |
| 6607958 | Semiconductor device and method of manufacturing the same Disclosed is a semiconductor device, comprising a semiconductor substrate, an insulating film and a gate electrode formed on the semiconductor substrate, source-drain regions formed in the semiconductor substrate, and a metal oxide layer formed selectivel... | 08/19/2003 |
| 6593450 | 2,7-aryl-9-substituted fluorenes and 9-substituted fluorene oligomers and polymers The invention relates to 2,7-substituted-9-substituted fluorenes and 9-substituted fluorene oligomers and polymers. The fluorenes, oligomers and polymers are substituted at the 9-position with two hydrocarbyl moieties which may optionally contain one or m... | 07/15/2003 |
| 6566210 | Method of improving gate activation by employing atomic oxygen enhanced oxidation The present invention provides a method of preparing a Si-based metal-insulator-semiconductor (MIS) transistor which prevents the polycrystalline grains of the gate conductor from getting significantly larger by reducing the thermal budget of the sidewall... | 05/20/2003 |
| 6563154 | Polysilicon layer having improved roughness after POCl3 doping An improved method for depositing the polysilicon layer from which a gate pedestal is later formed is described. Deposition takes place in two stages. Initially, the conventional deposition temperature of about 630° C. is used. Then, when the intended th... | 05/13/2003 |
| 6562687 | MIS transistor and method for making same on a semiconductor substrate The invention relates to an MIS transistor comprising a channel region (118), source (114) and drain (116) regions arranged on either side of the channel, and a gate (150) set closely above the channel region. According to the invention, the channel has a... | 05/13/2003 |
| 6559037 | Process for producing semiconductor device having crystallized film formed from deposited amorphous film A semiconductor device containing a polycrystalline silicon thin film wherein crystal grains of the silicon thin film have mainly a columnar structure and a crystal orientation of individual crystal grains is almost in a uniform direction can be produced ... | 05/06/2003 |
| 6548862 | Structure of semiconductor device and method for manufacturing the same A semiconductor device and a method for manufacturing the same are provided. The structure of a semiconductor device includes gate electrodes having a T-shaped structure comprised of first and second gate electrodes having low gate resistance and low para... | 04/15/2003 |
| 6507072 | Insulated gate field effect semiconductor device and forming method thereof In an insulated gate field effect semiconductor device, the gate electrode formed on the gate insulating film includes the first and second semiconductor layers as a double layer. An impurity for providing one conductivity type is not contained in first s... | 01/14/2003 |
| 6495890 | Field-effect transistor with multidielectric constant gate insulation layer A field-effect transistor comprises a semiconductor substrate, a gate insulation film formed selectively on the semiconductor substrate, a gate electrode formed on the gate insulation film, source/drain regions formed in surface portions of the semiconduc... | 12/17/2002 |
| 6489207 | Method of doping a gate and creating a very shallow source/drain extension and resulting semiconductor The present invention relates to a method of forming a very shallow source-drain (S/D) extension while simultaneously highly doping a very narrow polysilicon gate through to the gate dielectric interface. The invention also relates to the resulting semico... | 12/03/2002 |
| 6482709 | Manufacturing process of a MOS transistor A manufacturing method of a MOS transistor. A gate oxide layer and a polysilicon layer are successively formed on a substrate. A nitrogen ion implantation is performed to implant nitrogen ions into the contact region of the polysilicon layer with the gate... | 11/19/2002 |
| 6482725 | Gate formation method for reduced poly-depletion and boron penetration Depletion of dopant from polysilicon gate layers with attendant dopant penetration of underlying gate oxide layers of silicon-based MOS and CMOS transistor devices are reduced or substantially eliminated by a process wherein a thin, high-quality silicon o... | 11/19/2002 |
| 6475887 | Method of manufacturing semiconductor device A semiconductor device which can effectively prevent impurity diffusion in heat treatment for electrically activating the impurity, and a manufacturing method thereof are disclosed. In the semiconductor device, a diffusion preventing layer having a depth ... | 11/05/2002 |
| 6475842 | Process for gate oxide side-wall protection from plasma damage to form highly reliable gate dielectrics The present invention provides a method for manufacturing a semiconductor device. The method includes forming an oxidized portion of an initial gate structure and a sacrificial gate layer, and further includes removing the oxidized portion of the initial ... | 11/05/2002 |
| 6476462 | MOS-type semiconductor device and method for making same An MOS-type semiconductor device comprises two semiconductors separated by an insulator. The two semiconductors comprise monocrystal semiconductors, each having a crystallographic orientation with respect to the insulator (or other crystallographic/semico... | 11/05/2002 |
| 6476454 | Semiconductor device and method of manufacturing the same Disclosed is a semiconductor device, comprising a semiconductor substrate, an insulating film and a gate electrode formed on the semiconductor substrate, source-drain regions formed in the semiconductor substrate, and a metal oxide layer formed selectivel... | 11/05/2002 |
| 6441464 | Gate oxide stabilization by means of germanium components in gate conductor A semi-conductor device includes a silicon substrate. A gate oxide dielectric layer is on the silicon substrate. A gate conductor includes a relatively thin layer of germanium on the dielectric layer. A relatively thick layer of gate conductor material is... | 08/27/2002 |
| 6432779 | Selective removal of a metal oxide dielectric A method for forming a semiconductor device is disclosed in which a metal oxide gate dielectric layer is formed over a substrate. A gate electrode is then formed over the metal oxide layer thereby exposing a portion of the metal oxide layer. The exposed p... | 08/13/2002 |
| 6432763 | Field effect transistor having doped gate with prevention of contamination from the gate during implantation For fabricating a field effect transistor on a semiconductor substrate, a gate dielectric of the field effect transistor is formed on a semiconductor substrate. A doped gate electrode, which may be comprised of silicon germanium (SiGe) for example, is for... | 08/13/2002 |
| 6413841 | MOS type semiconductor device and manufacturing method thereof First, a polysilicon film is formed on a gate oxide film. Next, a polysilicon oxide film is formed on the polysilicon film. Thereafter, the polysilicon film is thermally treated to allow a crystal grain in the polysilicon film to grow from the gate oxide ... | 07/02/2002 |
| 6380055 | Dopant diffusion-retarding barrier region formed within polysilicon gate layer A diffusion-retarding barrier region is incorporated into the gate electrode to reduce the downward diffusion of dopant toward the gate dielectric. The barrier region is a nitrogen-containing diffusion retarding barrier region formed between two separatel... | 04/30/2002 |
| 6376323 | Fabrication of gate of P-channel field effect transistor with added implantation before patterning of the gate For fabricating a PMOS (P-channel Metal Oxide Semiconductor) field effect transistor on a semiconductor substrate, a layer of gate dielectric material containing nitrogen is deposited on the semiconductor substrate, and a layer of gate electrode material ... | 04/23/2002 |
| 6368926 | Method of forming a semiconductor device with source/drain regions having a deep vertical junction The present invention is directed to a method of forming source/drain regions in a semiconductor device. In one illustrative embodiment, the method comprises forming a gate stack above a semiconducting substrate, forming a recess in said substrate proxima... | 04/09/2002 |
| 6362033 | Self-aligned LDD formation with one-step implantation for transistor formation A method for forming a transistor is formed where a gate electrode of the transistor is formed over a substrate defining a gate channel portion of the substrate. A mask is also formed over the substrate, a portion of the mask extending over a first portio... | 03/26/2002 |
| 6337264 | Simplified method of patterning polysilicon gate in a semiconductor device including an oxime layer as a mask Polysilicon gates are formed with greater accuracy and consistency by depositing an antireflective layer of silicon oxime on the polysilicon layer before patterning. Embodiments also include depositing the polysilicon layer and the silicon oxime layer in ... | 01/08/2002 |
| 6313021 | PMOS device having a layered silicon gate for improved silicide integrity and enhanced boron penetration resistance The present invention provides a process for forming a sub-micron p-type metal oxide semiconductor (PMOS) structure on a semiconductor substrate. The process includes forming a gate oxide on the semiconductor substrate, forming a gate layer on the gate ox... | 11/06/2001 |
| 6306710 | Fabrication of a gate structures having a longer length toward the top for formation of a rectangular shaped spacer The gate structure of the MOSFET of the present invention is formed to have a longer length toward the top of the gate structure such that a spacer having a substantially rectangular shaped is formed at the sidewalls of the gate structure. For fabricating... | 10/23/2001 |
