Class 257/E21.196 - Final conductor next to insulator having lateral composition or doping variation, or being formed laterally by more than one deposition step (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.195. This subclass
No. of patents: 87
Last issue date: 05/15/2007

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Number	Title	Issue Date
7217624	Non-volatile memory device with conductive sidewall spacer and method for fabricating the same The present invention relates to a non-volatile memory device having conductive sidewall spacers and a method for fabricating the same. The non-volatile memory device includes: a substrate; a gate insulation layer formed on the substrate; a gate structure formed on ...	05/15/2007
6696725	Dual-gate MOSFET with channel potential engineering A semiconductor device with reduced hot carrier injection and punch through is formed with a dual gate electrode comprising edge conductive portions, a central conductive portion, and dielectric sidewall spacers formed between the edge conductive portions...	02/24/2004
6686295	Anisotropic etch method A method to anisotropically etch an oxide/silicide/poly sandwich structure on a silicon wafer substrate in situ, that is, using a single parallel plate plasma reactor chamber and a single inert cathode, with a variable gap between cathode and anode. This ...	02/03/2004
6680224	Methods of forming and operating field effect transistors having gate and sub-gate electrodes Field effect transistors include a semiconductor substrate having a channel region of first conductivity type therein extending adjacent a surface thereof. Source and drain regions of second conductivity type are also provided at opposite ends of the chan...	01/20/2004
6639288	Semiconductor device with a particular conductor arrangement A tungsten nitride (6b) is provided also on side surface of a tungsten (6c), to increase an area where the tungsten (6c) and the tungsten nitride (6b) are in contact with each other. On a gate insulating film (2), a polysilicon side wall (5) having high a...	10/28/2003
6613654	Fabrication of semiconductor devices with transition metal boride films as diffusion barriers An integrated circuit has a multi-layer stack such as a gate stack or a digit line stack disposed on a layer comprising silicon. A conductive film is formed on the transition metal boride layer. A process for fabricating such devices can include forming t...	09/02/2003
6614082	Fabrication of semiconductor devices with transition metal boride films as diffusion barriers An integrated circuit has a multi-layer stack such as a gate stack or a digit line stack disposed on a layer comprising silicon. A conductive film is formed on the transition metal boride layer. A process for fabricating such devices can include forming t...	09/02/2003
6528404	Semiconductor device and fabrication method thereof A semiconductor device and a fabrication method thereof that can improve performance and reliability by restricting the generation of a hot carrier effect is disclosed. Such a semiconductor device includes: a semiconductor substrate; a gate insulating lay...	03/04/2003
6528399	MOSFET transistor with short channel effect compensated by the gate material A MOSFET transistor comprising a gate made of silicon-germanium alloy, formed on a single crystal silicon substrate by means of a thin insulating layer, and drain and source regions implanted in the substrate on each side of the gate, characterized in tha...	03/04/2003
6468843	MIS semiconductor device having an LDD structure and a manufacturing method therefor It is intended to provide a method of forming a gate overlap lightly doped impurity region (GOLD). After a gate insulating film is formed by a material mainly made of silicon oxide and a gate electrode is formed with, for instance, silicon, lightly doped ...	10/22/2002
6461976	Anisotropic etch method A method to anisotropically etch an oxide/silicide/poly sandwich structure on a silicon wafer substrate in situ, that is, using a single parallel plate plasma reactor chamber and a single inert cathode, with a variable gap between cathode and anode. This ...	10/08/2002
6448613	Fabrication of a field effect transistor with minimized parasitic Miller capacitance A field effect transistor is fabricated to have a drain overlap and a source overlap to minimize series resistance between the gate and the drain and between the gate and the source of the field effect transistor. The parasitic Miller capacitance formed b...	09/10/2002
6407436	Semiconductor device with abrupt source/drain extensions with controllable gate electrode overlap A method for forming source/drain extensions with gate overlap. An oxide layer is formed on a semiconductor substrate and a gate structure on the semiconductor substrate. First, sidewall spacer regions are formed on sides of the gate structure. Second spa...	06/18/2002
6312995	MOS transistor with assisted-gates and ultra-shallow "Psuedo" source and drain extensions for ultra-large-scale integration A MOS transistor and a method of fabricating the same for Ultra Large Scale Integration applications includes a composite gate structure. The composite gate structure is comprised of a main gate electrode and two assisted-gate electrodes disposed adjacent...	11/06/2001
6306738	Modulation of gate polysilicon doping profile by sidewall implantation A device and method to modulate a gate polysilicon doping profile by performing a sidewall implantation. The method includes forming a gate on a substrate and implanting ions through a sidewall in the gate. The ion implantation is performed by projecting ...	10/23/2001
6303995	Sidewall structure for metal interconnect and method of making same Disclosed is an integrated circuit structure having one or more metal lines thereon with metal line sidewall retention structures formed on the sides of the metal lines. The metal line sidewall retention structures comprise a material sufficiently hard to...	10/16/2001
6300207	Depleted sidewall-poly LDD transistor The present invention is directed to a metal oxide semiconductor transistor having a fully overlapped lightly doped drain (LDD) structure which offers the advantages of conventional fully overlapped LDD transistors but which significantly reduces the drai...	10/09/2001
6300177	Method to form transistors with multiple threshold voltages (VT) using a combination of different work function gate materials A method of forming a gate electrode, comprising the following steps. A semiconductor substrate having an overlying patterned layer exposing a portion of the substrate within active area and patterned layer opening. The patterned layer having exposed side...	10/09/2001
6284577	MIS semiconductor device having an LDD structure and a manufacturing method therefor It is intended to provide a method of forming a gate overlap lightly doped impurity region (GOLD). After a gate insulating film is formed by a material mainly made of silicon oxide and a gate electrode is formed with, for instance, silicon, lightly doped ...	09/04/2001
6281086	Semiconductor device having a low resistance gate conductor and method of fabrication the same A semiconductor device and a method of fabricating the same is provided, wherein the semiconductor device exhibits a lower gate delay time when compared to that of a conventional semiconductor device. The reduction of gate delay time is achieved by provid...	08/28/2001
6281062	MOS semiconductor device with self-aligned punchthrough stops and method of fabrication A novel high-speed, highly reliable VSLI manufacturable metal oxide semiconductor transistor with self-aligned punchthrough stops. A gate insulating layer is formed on a substrate having a first concentration of a first conductivity type. An inner gate el...	08/28/2001
6274446	Method for fabricating abrupt source/drain extensions with controllable gate electrode overlap A method for forming source/drain extensions with gate overlap. An oxide layer is formed on a semiconductor substrate and a gate structure on the semiconductor substrate. First, sidewall spacer regions are formed on sides of the gate structure. Second spa...	08/14/2001
6255175	Fabrication of a field effect transistor with minimized parasitic Miller capacitance A field effect transistor is fabricated to have a drain overlap and a source overlap to minimize series resistance between the gate and the drain and between the gate and the source of the field effect transistor. The parasitic Miller capacitance formed b...	07/03/2001
6251760	Semiconductor device and its wiring and a fabrication method thereof A semiconductor device and a wiring therefor and a fabrication method thereof are disclosed, which are capable of providing a good current driving capability without degrading the characteristic of the semiconductor device by overcoming the problems encou...	06/26/2001
6248638	Enhancements to polysilicon gate The conductivity of gate structures can be improved by siliciding the entire gate. Additionally, silicon sidewalls can be added to the gate after the "smiling" oxidation, but before silicidation, which provides a new tool for drain profile engineering....	06/19/2001
6236093	Semiconductor device including gate electrode having polymetal structure and method of manufacturing of the same According to the present invention, a gate electrode having a polymetal structure, that is, a lamination structure of a polysilicon film formed via a gate insulating film on a semiconductor substrate, and a refractory metal film. An electroconductive side...	05/22/2001
6229198	Non-uniform gate doping for reduced overlap capacitance A transistor is formed comprising a gate electrode with a non-uniform impurity profile increasing from the drain side to the source side, thereby reducing the overlap capacitance between the gate electrode and drain region. In addition, the transverse ele...	05/08/2001
6225669	Non-uniform gate/dielectric field effect transistor A field effect transistor (FET) structure, and method for making the same, which further suppresses short-channel effects based on variations within the gate dielectric itself. The FET structure utilizes non-uniform gate dielectrics to alter the vertical ...	05/01/2001
6218276	Silicide encapsulation of polysilicon gate and interconnect Provided is a method of forming a silicide layer on the top and sidewall surfaces of a polysilicon gate/interconnect in a MOS transistor and on the exposed surfaces of the source and drain regions of the transistor. Devices produced according to the prese...	04/17/2001
6200839	Methods of forming thin film transistors A method of forming a thin film transistor includes, a) forming a thin film transistor layer of semiconductive material; b) providing a gate operatively adjacent the thin film transistor layer; c) forming at least one electrically conductive sidewall spac...	03/13/2001
6187676	Integrated circuit insulated electrode forming methods using metal silicon nitride layers, and insulated electrodes so formed Insulated electrodes are formed by first forming on an integrated circuit substrate, an insulating layer, a conductive layer on the insulating layer, and a metal silicide layer on the conductive layer, and then forming a metal silicon nitride layer on the...	02/13/2001
6187657	Dual material gate MOSFET technique This invention comprises a new technique to realize a dual material gate MOSFET. The inventive technique is base upon an asymmetric oxide spacer formation and a self-aligned silicide formation. The asymmetric oxide spacer on the sidewall of the drain side...	02/13/2001
6166398	Thin film transistors A method of forming a thin film transistor includes, a) forming a thin film transistor layer of semiconductive material; b) providing a gate operatively adjacent the thin film transistor layer; c) forming at least one electrically conductive sidewall spac...	12/26/2000
6153534	Method for fabricating a dual material gate of a short channel field effect transistor A dual material gate is effectively fabricated for a field effect transistor having a short channel length of submicron and nanometer dimensions such that disadvantageous short channel effects are minimized. Generally, the method of the present invention ...	11/28/2000
6133156	Anisotropic etch method A method to anisotropically etch an oxide/silicide/poly sandwich structure on a silicon wafer substrate in situ, that is, using a single parallel plate plasma reactor chamber and a single inert cathode, with a variable gap between cathode and anode. This ...	10/17/2000
6110783	Method for forming a notched gate oxide asymmetric MOS device A method for making an asymmetric MOS device having a notched gate oxide wherein a region of the gate oxide adjacent to either the source or drain is thinner than the remainder of the gate oxide. The resulting MOS device includes a channel under the notch...	08/29/2000
6100143	Method of making a depleted poly-silicon edged MOSFET structure A field effect transistor with reduced corner device problems comprises source and drain regions formed in a substrate, a channel region between the source and drain regions, isolation regions in the substrate adjacent the source, channel and drain region...	08/08/2000
6096641	Method of manufacturing semiconductor device A tungsten nitride (6b) is provided also on side surface of a tungsten (6c), to increase an area where the tungsten (6c) and the tungsten nitride (6b) are in contact with each other. On a gate insulating film (2), a polysilicon side wall (5) having high a...	08/01/2000
6091118	Semiconductor device having reduced overlap capacitance and method of manufacture thereof A semiconductor device and process for manufacture thereof is disclosed in which a gate electrode with reduced overlap capacitance is formed by forming a gate electrode on a surface of a semiconductor and doping edge portions of the gate electrode with a ...	07/18/2000
6081010	MOS semiconductor device with self-aligned punchthrough stops and method of fabrication A novel high-speed, highly reliable VLSI manufacturable metal oxide semiconductor transistor with self-aligned punchthrough stops. A gate insulating layer is formed on a substrate having a first concentration of a first conductivity type. An inner gate el...	06/27/2000

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Class 257/E21.196 - Final conductor next to insulator having lateral composition or doping variation, or being formed laterally by more than one deposition step (EPO)