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| Number | Title | Issue Date |
| 7199043 | Method of forming copper wiring in semiconductor device Disclosed in a method of forming a copper wiring in a semiconductor device. A copper layer buries a damascene pattern in which an interlayer insulating film of a low dielectric constant. The copper layer is polished by means of a chemical mechanical polishing proces... | 04/03/2007 |
| 7129170 | Method for depositing and etching ruthenium layers The present invention provides a method for purifying ruthenium sources to obtain high purity ruthenium metal and form a ruthenium metal pattern on a semiconductor substrate without the need for high temperature processing or a complex series of wet processes. A gas... | 10/31/2006 |
| 6441464 | Gate oxide stabilization by means of germanium components in gate conductor A semi-conductor device includes a silicon substrate. A gate oxide dielectric layer is on the silicon substrate. A gate conductor includes a relatively thin layer of germanium on the dielectric layer. A relatively thick layer of gate conductor material is... | 08/27/2002 |
| 6284609 | Method to fabricate a MOSFET using selective epitaxial growth to form lightly doped source/drain regions A new method of fabricating a sub-quarter micron MOSFET device is achieved. A semiconductor substrate is provided. Isolation regions are formed in this substrate. An oxide layer is provided overlying both the substrate and the isolation regions. The oxide... | 09/04/2001 |
| 6281532 | Technique to obtain increased channel mobilities in NMOS transistors by gate electrode engineering A method of modifying the mobility of a transistor. First, a transistor having a gate is formed. A substance is then implanted in the gate. The transistor is annealed such that the implanted substance forms at least one void in the transistor's gate.... | 08/28/2001 |
| 5885889 | Process of fabricating semiconductor device having doped polysilicon layer without segregation of dopant impurity An intentionally undoped amorphous silicon layer, a phosphorous doped amorphous silicon layer and a tungsten silicide layer are successively laminated on a gate oxide layer, and are patterned into a gate electrode of a field effect transistor; while a pho... | 03/23/1999 |
| 5843827 | Method of reducing dielectric damage from plasma etch charging A method of suppressing damage to gate dielectrics by reducing the electrical field across the gate dielectric during plasma etching, photoresist stripping, or plasma assisted deposition of the overlying conductor to be etched. Openings in the gate oxide ... | 12/01/1998 |
| 5801399 | Semiconductor device with antireflection film A stress relaxation layer is inserted between an electrode layer and an antireflection layer to relax a stress imparted from one of the electrode and antireflection layers to the other. A semiconductor device is provided which can suppress separation of t... | 09/01/1998 |
| 5512497 | Method of manufacturing a semiconductor integrated circuit device Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channe... | 04/30/1996 |
| 5413966 | Shallow trench etch A trench mask is formed of two dissimilar layers of material deposited over a substrate. The lower of the two layers is an insulating layer such as silicon dioxide or silicon nitride, or combinations of both, and the upper of the two layers is doped or un... | 05/09/1995 |
| 5362356 | Plasma etching process control A passive, in-line method of monitoring film removal (or deposition) during plasma etching (or deposition) based on interference phenomena is disclosed. Plasma emission intensity is monitored at a selected wavelength, without additional illuminating appar... | 11/08/1994 |
| 5354699 | Method of manufacturing semiconductor integrated circuit device Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channe... | 10/11/1994 |
| 5328864 | Method of doping gate electrodes discretely with either P-type or N-type impurities to form discrete semiconductor regions The present invention relates to a method of manufacturing a semiconductor device. In a semiconductor substrate formed with a first semiconductor region of P-type and a second semiconductor region of N-type and an insulating film formed between and extend... | 07/12/1994 |
| 4737474 | Silicide to silicon bonding process A process for forming a bonding layer comprising amorphous silicon, titanium, chromium, or tungsten, between the silicide and the N+ polysilicon layer is disclosed. The bonding layer is preferably less than 50 nm. thick. After the bonding layer is deposit... | 04/12/1988 |
