Class 257/E21.179 - Floating or plural gate structure (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.177. This subclass
No. of patents: 100
Last issue date: 10/21/2008

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Number	Title	Issue Date
7439121	Dielectric film and method of forming it, semiconductor device, non-volatile semiconductor memory device, and production method for semiconductor device In a film formation method of a semiconductor device including a plurality of silicon-based transistors or capacitors, there exist hydrogen at least in a part of the silicon surface in advance, and the film formation method removes the hydrogen by exposing the silic...	10/21/2008
7439573	Semiconductor device including transistor with composite gate structure and transistor with single gate structure, and method for manufacturing the same A semiconductor device comprises a first transistor having a composite gate structure containing a lamination of a first polycrystalline silicon film, an interlayer insulating film, and a second polycrystalline silicon film; and a second transistor having a single g...	10/21/2008
7432156	Memory device and methods for its fabrication A semiconductor memory device and a method for its fabrication are provided. In accordance with one embodiment of the invention the method comprises the steps of forming a gate insulator and a gate electrode overlying a semiconductor substrate. The gate insulator is...	10/07/2008
7422960	Method of forming gate arrays on a partial SOI substrate The invention includes methods for utilizing partial silicon-on-insulator (SOI) technology in combination with fin field effect transistor (finFET) technology to form transistors particularly suitable for utilization in dynamic random access memory (DRAM) arrays. Th...	09/09/2008
7419875	Shallow trench isolation in floating gate devices The present invention provides a method for manufacturing a floating gate type semiconductor device on a substrate having a surface (2), and a device thus manufactured. The method comprises:—forming, on the substrate surface, a stack comprising an insulatin...	09/02/2008
7419879	Transistor having gate dielectric layer of partial thickness difference and method of fabricating the same A transistor having a gate dielectric layer of partial thickness difference and a method of fabricating the same are provided. The method includes forming a gate dielectric layer having a main portion with a relatively thin thickness formed on a semiconductor substr...	09/02/2008
7417280	Method and apparatus for a flash memory device comprising a source local interconnect A method for forming a flash memory device having a local interconnect connecting source regions of a plurality of transistors within a sector allows for a highly selective wet etch of a dielectric region overlying the source region. An embodiment of the method comp...	08/26/2008
7414284	Nonvolatile semiconductor memory and manufacturing method thereof A nonvolatile semiconductor memory includes a trench isolation provided in a semiconductor substrate and an interlayer insulator provided on the semiconductor substrate. The trench isolation defines an active area extending in a first direction at the semiconductor ...	08/19/2008
7411243	Nonvolatile semiconductor device and method of fabricating the same A nonvolatile semiconductor device and a method of fabricating the same are provided. The nonvolatile semiconductor device includes a semiconductor body formed on a substrate to be elongated in one direction and having a cross section perpendicular to a main surface...	08/12/2008
7410869	Method of manufacturing a semiconductor device In a method of manufacturing a semiconductor device such as a flash memory device, an insulating pattern having an opening is formed to partially expose a surface of a substrate. A first silicon layer is formed on the exposed surface portion of the substrate and the...	08/12/2008
7407855	Method of producing semiconductor element and nonvolatile semiconductor memory produced by this method In a first embodiment, Tetraethyl Orthosilicate Si(OC2H5)4 is used at the process temperature of 650° C.±5° C. as film forming material, to decrease crystal defects occurring during deposition. In a second embodiment, annealing is carried out in sparse oxygen gas...	08/05/2008
7405110	Methods of forming implant regions relative to transistor gates The invention includes methods of forming implant regions between and/or under transistor gates. In one aspect, a pair of transistor gates is partially formed, and a layer of conductive material is left extending between the transistor gates. A dopant is implanted t...	07/29/2008
7405126	Memory device with quantum dot and method for manufacturing the same Provided is a memory device formed using quantum devices and a method for manufacturing the same. A memory device includes a substrate; a source region and a drain region formed in the substrate so as to be separated from each other by a predetermined interval. A me...	07/29/2008
7399678	Method for reading an array of multi-bit ROM cells with each cell having bi-directional read A array of multi-bit Read Only Memory (ROM) cells is in a semiconductor substrate of a first conductivity type with a first concentration. Each ROM cell has a first and second regions of a second conductivity type spaced apart from one another in the substrate. A ch...	07/15/2008
7397079	Non-volatile memory device and methods of forming the same A non-volatile memory device includes a control gate electrode disposed on a substrate with a first insulation layer interposed therebetween and a floating gate disposed in a hole exposing substrate through the control gate electrode and the first insulation layer. ...	07/08/2008
7396722	Memory device with reduced cell area The present invention provides for a memory device comprising a bulk substrate. A first lightly doped region is formed in the bulk substrate. A first active region is formed in the first lightly doped region. A second lightly doped region is formed in the bulk subst...	07/08/2008
7391078	Non-volatile memory and manufacturing and operating method thereof A non-volatile memory is provided. A substrate having a plurality of trenches and a plurality of select gates is provided. The trenches are arranged in parallel and extend in a first direction. Each of the select gates is disposed on the substrate between two adjace...	06/24/2008
7378314	Source side injection storage device with control gates adjacent to shared source/drain and method therefor A storage device has a two bit cell in which the select electrode is nearest the channel between two storage layers. Individual control electrodes are over individual storage layers. Adjacent cells are separated by a doped region that is shared between the adjacent ...	05/27/2008
7374995	Nonvolatile semiconductor memory device A nonvolatile semiconductor memory device including a memory cell and a selection transistor, and the memory cell includes a floating gate formed on a semiconductor substrate via a first gate insulation film, a pair of first diffusion layers positioned on the opposi...	05/20/2008
7371672	Semiconductor device and method of manufacturing the same A method of manufacturing a semiconductor device includes removing a low-resistivity metal film, conductive layer, third insulating film and an upper part of the electrode layer in a gate electrode isolation region with a gate forming pattern serving as a mask, form...	05/13/2008
7368346	Method for forming gate structure in flash memory device Device isolation insulation layers passing through an insulation layer and a substrate, are formed, and a portion of them is removed. The insulation layer is removed. A gate oxide layer and a first conductive layer sequentially formed over the device isolation insul...	05/06/2008
7368338	Nonvolatile memory and manufacturing method thereof Memory elements, switching elements, and peripheral circuits to constitute a nonvolatile memory are integrally formed on a substrate by using TFTs. Since semiconductor active layers of memory element TFTs are thinner than those of other TFTs, impact ionization easil...	05/06/2008
7364970	Method of making a multi-bit non-volatile memory (NVM) cell and structure A multi-bit non volatile memory cell includes a first floating gate sidewall spacer structure and a second floating gate sidewall spacer structure physically separated from the first floating gate sidewall spacer structure. Each floating gate sidewall spacer structu...	04/29/2008
7361553	Semiconductor device manufacturing method A memory transistor and a high breakdown voltage MOS transistor are easily formed on the same semiconductor substrate without changing the operational characteristics of the memory transistor. The process of forming the tunnel insulation film of the memory transisto...	04/22/2008
7361535	Liquid crystal display device having polycrystalline TFT and fabricating method thereof A thin film transistor includes a substrate, a crystallized semiconductor layer formed over the substrate having a channel region, low-density impurity regions and high-density impurity regions, a gate insulating layer formed on the crystallized semiconductor layer,...	04/22/2008
7361545	Field effect transistor with buried gate pattern A field effect transistor includes a buried gate pattern that is electrically isolated by being surrounded by a tunneling insulating film. The field effect transistor also includes a channel region that is floated by source and drain regions, a gate insulating film,...	04/22/2008
7358129	Nonvolatile semiconductor memory device and a method of the same A reduction in size nonvolatile semiconductors for use in a memory device and an increase in the capacity thereof are promoted. Each memory cell of a flash memory is provided with a field effect transistor having a first gate insulator film formed on a p-type well, ...	04/15/2008
7358134	Split gate flash memory cell and manufacturing method thereof A split gate flash memory cell includes a substrate having a device isolation structure; a selective gate structure disposed on the substrate; an interlayer dielectric layer having an opening disposed on the substrate, wherein the opening exposes a portion of the se...	04/15/2008
7348267	Flash memory and method of fabricating the same A method of fabricating a flash memory device produces a device that has a small cell area and yet a high coupling ratio. First, a basic structure is provided that includes a substrate, a field isolation film protruding from the substrate, and floating gates dispose...	03/25/2008
7348237	NOR flash memory cell with high storage density Structures and methods for NOR flash memory cells, arrays and systems are provided. The NOR flash memory cell includes a vertical floating gate transistor extending outwardly from a substrate. The floating gate transistor having a first source/drain region, a second...	03/25/2008
7344944	Non-volatile memory device and fabricating method thereof A non-volatile memory device comprises a gate line that includes a gate dielectric layer, a bottom gate pattern, an inter-gate dielectric and a top gate pattern, which are sequentially stacked. The width of the inter-gate dielectric is narrower than that of the bott...	03/18/2008
7329578	Method of forming floating-gate tip for split-gate flash memory process A split-gate flash memory process for improving sharpness and height of a floating-gate tip has steps as follows. Using a dry etching process, a trench is formed in the first polysilicon layer through the pattern opening. An oxide layer is then deposited on the firs...	02/12/2008
7323384	Method of manufacturing semiconductor device A method of manufacturing a semiconductor memory device comprises the steps of: preparing a semiconductor substrate having a gate insulation film and a gate electrode, the gate insulation film being formed on a predetermined active region in the semiconductor substr...	01/29/2008
7319058	Fabrication method of a non-volatile memory A fabrication method for a non-volatile memory is provided. To fabricate the non-volatile memory, a plurality of first trenches and second trenches are formed in a substrate, wherein the second trenches are disposed above the first trenches and cross over the first ...	01/15/2008
7309632	Method for fabricating a nonvolatile memory cell A method of fabricating a nonvolatile memory cell includes providing a substrate with a trench, with a sidewall where a tunnel oxide layer and a floating gate are successively formed, forming a control gate in the trench, performing a high density plasma deposition ...	12/18/2007
7303960	Method for fabricating flash memory device A method for fabricating a flash memory device including the steps of: providing a substrate having thereon a gate with therein a control gate; lining the substrate and the gate with a liner; forming a silicon layer on the liner; forming a sacrificing layer on the s...	12/04/2007
7303959	Bottom-gate SONOS-type cell having a silicide gate A bottom-gate thin film transistor having a silicide gate is described. This transistor is advantageously formed as SONOS-type nonvolatile memory cell, and methods are described to efficiently and robustly form a monolithic three dimensional memory array of such cel...	12/04/2007
7303957	Method of fabricating a flash memory device A method of fabricating a flash memory device using a process for forming a self-aligned floating gate is provided. The method comprises forming mask patterns on a substrate, etching the substrate using the mask patterns as an etch mask to form a plurality of trench...	12/04/2007
7297592	Semiconductor memory with data retention liner A manufacturing method for a dual bit flash memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer with the depositing performed without using ammonia at an ultra-slow deposition rate. First and second bitlines are impl...	11/20/2007
7294549	Vertical floating gate transistor A floating gate transistor has been described that includes source and drain regions that are fabricated on different horizontal planes. A floating gate and a control gate are fabricated vertically to control current conducted through the transistor. The control gat...	11/13/2007

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Class 257/E21.179 - Floating or plural gate structure (EPO)