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| Number | Title | Issue Date |
| 7381657 | Biased pulse DC reactive sputtering of oxide films A biased pulse DC reactor for sputtering of oxide films is presented. The biased pulse DC reactor couples pulsed DC at a particular frequency to the target through a filter which filters out the effects of a bias power applied to the substrate, protecting the pulsed... | 06/03/2008 |
| 7375024 | Method for fabricating metal interconnection line with use of barrier metal layer formed in low temperature The present invention relates to a method for fabricating a metal interconnection line with use of a barrier metal layer formed in a low temperature. The method includes the steps of: forming an inter-layer insulation layer on a substrate; etching predetermined regi... | 05/20/2008 |
| 7256121 | Contact resistance reduction by new barrier stack process The present invention provides a method for forming an interconnect on a semiconductor substrate 100. The method includes forming an opening 230 over an inner surface of the opening 130, the depositing forming a reentrant profile near a top port... | 08/14/2007 |
| 7214619 | Method for forming a barrier layer in an integrated circuit in a plasma with source and bias power frequencies applied through the workpiece A barrier layer is formed in an integrated circuit by providing a metal target near a ceiling of the chamber and a wafer support pedestal facing the target near a floor of the chamber. A process gas is introduced into the vacuum chamber. A target-sputtering plasma i... | 05/08/2007 |
| 7071096 | Method of forming a conductive barrier layer within critical openings by a final deposition step after a re-sputter deposition In forming a thin conductive layer in an interconnect structure by sputter deposition including a re-sputtering step, a flash deposition step is performed after the re-sputtering step to provide a sufficient layer thickness at critical locations, such as at position... | 07/04/2006 |
| 6699789 | Metallization process to reduce stress between Al-Cu layer and titanium nitride layer Embodiments of the present invention are directed to a metallization process for reducing the stress existing between the Al--Cu layer and the titanium nitride (TiN) layer, and solving the galvanic problem. The process does so by cooling the wafer in the ... | 03/02/2004 |
| 6696360 | Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow A method for forming conductive contacts and interconnects in a semiconductor structure, and the resulting conductive components are provided. In particular, the method is used to fabricate single or dual damascene copper contacts and interconnects in int... | 02/24/2004 |
| 6692995 | Physically deposited layer to electrically connect circuit edit connection targets Disclosed is a layer to electrically connect targets during a circuit edit of an integrated circuit and systems and methods for forming the layer. The layer contains a conductive material, such as gold or another metal, which has been physically deposited... | 02/17/2004 |
| 6688584 | Compound structure for reduced contact resistance Various embodiments of the invention described herein reduce contact resistance to a silicon-containing material using a first refractory metal material overlying the silicon-containing material and a second refractory metal material overlying the first r... | 02/10/2004 |
| 6680249 | Si-rich surface layer capped diffusion barriers A copper interconnect having a transition metal-nitride barrier (106) with a thin metal-silicon-nitride cap (108). A transition metal-nitride barrier (106) is formed over the structure. Then the barrier (106) is annealed in a Si-containing ambient to form... | 01/20/2004 |
| 6673704 | Semiconductor device and method of manufacturing the same A method of manufacturing semiconductor device which comprises the steps of forming an insulating film on an Si substrate provided with a wiring layer, forming a contact hole connected to the wiring layer and a wiring groove in the insulating film, fillin... | 01/06/2004 |
| 6673716 | Control of the deposition temperature to reduce the via and contact resistance of Ti and TiN deposited using ionized PVD techniques A method of depositing thin films comprising Ti and TiN within vias and trenches having high aspect ratio openings. The Ti and TiN layers are formed on an integrated circuit substrate using a Ti target in a non-nitrided mode in a hollow cathode magnetron ... | 01/06/2004 |
| 6673724 | Pulsed-mode RF bias for side-wall coverage improvement The present invention provides a method and apparatus for achieving conformal step coverage of one or more materials on a substrate using sputtered ionized material. A target provides a source of material to be sputtered by a plasma and then ionized by an... | 01/06/2004 |
| 6670267 | Formation of tungstein-based interconnect using thin physically vapor deposited titanium nitride layer A tungsten-based interconnect is created by first providing a structure with an opening (464/470) in a structure and then rounding the top edge of the opening. A titanium nitride layer (150) is physically vapor deposited to a thickness less than 30 nm, ty... | 12/30/2003 |
| 6667231 | Method of forming barrier films for copper metallization over low dielectric constant insulators in an integrated circuit An integrated circuit structure and method of making the same is disclosed, in which the adhesion of copper conductors (12, 22) to a low-dielectric constant insulating layer (10, 16) is improved. During the fabrication of the structure, exposed surfaces o... | 12/23/2003 |
| 6664633 | Alkaline copper plating A method for depositing a metal conduction layer in a feature of a substrate is provided. The method includes forming the feature in the substrate, the feature having a width dimension of less than about a tenth of a micron. A barrier layer is deposited o... | 12/16/2003 |
| 6656836 | Method of performing a two stage anneal in the formation of an alloy interconnect A method of performing a two stage anneal in the formation of an alloy interconnect can include forming a via aperture in a dielectric layer where the via aperture provides an area for formation of a via, providing a seed layer along lateral side walls of... | 12/02/2003 |
| 6652718 | Use of RF biased ESC to influence the film properties of Ti and TiN A method of depositing thin films comprising Ti and TiN within vias and trenches having high aspect ratio openings of 6:1 is disclosed. The Ti and TiN layers are formed on an integrated circuit substrate using a Ti target in a non-nitrided mode in a hollo... | 11/25/2003 |
| 6649449 | Methods of forming physical vapor deposition target/backing plate assemblies The invention encompasses PVD target/backing plate assemblies which include a PVD target having a surface, and a bonding layer on the surface. The bonding layer has a different composition than the target surface, and a backing plate is provided to be sep... | 11/18/2003 |
| 6650017 | Electrical wiring of semiconductor device enabling increase in electromigration (EM) lifetime A method for manufacturing a semiconductor device having on a silicon substrate semiconductor elements and aluminum (Al) alloy wiring leads as electrically connected thereto is disclosed. The method includes the steps of forming on the silicon substrate a... | 11/18/2003 |
| 6646302 | Embedded metal nanocrystals Low resistance metal/semiconductor and metal/insulator contacts incorporate metal nanocrystals embedded in another metal having a different work function. The contacts are fabricated by placing a wetting layer of a first metal on a substrate, which may be... | 11/11/2003 |
| 6638856 | Method of depositing metal onto a substrate A method for depositing a metal layer on a substrate includes the steps of depositing a first metal layer at a first deposition temperature; depositing a second metal layer on the first metal layer at a second deposition temperature higher than the first ... | 10/28/2003 |
| 6638580 | Apparatus and a method for forming an alloy layer over a substrate using an ion beam One embodiment of the invention involves introducing at least two metals into a chamber for forming an alloy layer over a substrate. This is accomplished by a variety of methods. In one embodiment, at least two metals are mixed and introduced into a chamb... | 10/28/2003 |
| 6627543 | Low-temperature sputtering system and method for salicide process Disclosed are methods and systems for forming salicide, in which a semiconductor substrate is provided with at least one exposed silicon surface. The semiconductor substrate is placed into a sputtering chamber. A silicide-forming metal layer, formed of a ... | 09/30/2003 |
| 6627547 | Hot metallization process The invention enables a layer of metal to be formed on a substrate with few or no voids formed in the layer, with increased throughput and without raising the temperature of the substrate to a level that may damage the substrate. A layer of metal can be f... | 09/30/2003 |
| 6627056 | Method and apparatus for ionized plasma deposition A system for performing PVD of metallic nitride(s) is disclosed. The improved performance is provided by a method of increasing the partial pressures of nitrogen or other active gases near the wafer surface through initial introduction of the argon or oth... | 09/30/2003 |
| 6624073 | Optimized TaCN thin film diffusion barrier for copper metallization A new method of forming a tantalum carbide nitride diffusion barrier layer having optimized nitrogen concentration for improved thermal stability is described. A contact region is provided in a substrate. A via is opened through an insulating layer to the... | 09/23/2003 |
| 6614116 | Buried digit line stack and process for making same A process of making a buried digit line stack is disclosed. The process includes forming a silicon-lean metal silicide first film over a polysilicon plug, followed by a silicide compound barrier second film. The silicide compound barrier second film is co... | 09/02/2003 |
| 6610597 | Method of fabricating a semiconductor device A semiconductor manufacturing process is disclosed that may form a contact structure with a tungsten plug. A contact structure hole may be adequately filled with tungsten, while avoiding plug loss, increased resistance and/or trenching, that can result fr... | 08/26/2003 |
| 6610184 | Magnet array in conjunction with rotating magnetron for plasma sputtering An array of auxiliary magnets is disclosed that is positioned along sidewalls of a magnetron sputter reactor on a side towards the wafer from the target. The magnetron preferably is a small, strong one having a stronger outer pole of a first magnetic pola... | 08/26/2003 |
| 6602788 | Process for fabricating an interconnect for contact holes A process for fabricating an interconnect for contact holes includes forming contact holes in an insulation layer leading to a first interconnect layer, cleaning the hole surface, forming a barrier layer on the hole surface, forming an AlGeCu-containing s... | 08/05/2003 |
| 6582569 | Process for sputtering copper in a self ionized plasma A DC magnetron sputter reactor for sputtering copper, its method of use, and shields and other parts promoting self-ionized plasma (SIP) sputtering, preferably at pressures below 5 milliTorr, preferably below 1 milliTorr. Also, a method of coating copper ... | 06/24/2003 |
| 6569785 | Semiconductor integrated circuit device having internal tensile and internal compression stress A semiconductor device has a structure that is capable of reducing warping of a semiconductor wafer when the semiconductor device is manufactured. The semiconductor device is manufactured by a method including the steps for forming an interlayer dielectri... | 05/27/2003 |
| 6555465 | Multi-layer wiring structure of integrated circuit and manufacture of multi-layer wiring A first wiring layer is formed on an insulating film. The first wiring layer is formed by sequentially laminating a barrier layer, an Al alloy layer, and an antireflection layer. The antireflection layer is formed by sequentially laminating a Ti layer, a ... | 04/29/2003 |
| 6552388 | Hafnium nitride gate dielectric A field effect semiconductor device comprising a high permittivity hafnium (or hafnium-zirconium) nitride gate dielectric and a method of forming the same are disclosed herein. The device comprises a silicon substrate 20 having a semiconducting channel re... | 04/22/2003 |
| 6541375 | DC sputtering process for making smooth electrodes and thin film ferroelectric capacitors having improved memory retention A ferroelectric thin film capacitor has smooth electrodes permitting comparatively stronger polarization, less fatigue, and less imprint, as the ferroelectric capacitor ages. The smooth electrode surfaces are produced by DC reactive sputtering.... | 04/01/2003 |
| 6537901 | Method of manufacturing a transistor in a semiconductor device There is disclosed a method of manufacturing a transistor in a semiconductor device. The present invention forms a Ta film or a TaNx film at a low temperature or forms a first TaNx film in which the composition(x) of nitrogen is 0.45~0.55, on a gate insul... | 03/25/2003 |
| 6515843 | Semiconductor capacitive device The present invention relates to semiconductor techniques using high dielectric oxides, more specifically to a thin film forming method for forming a thin film which is suitable as the electrodes of the oxide high dielectrics, a capacitor device using the... | 02/04/2003 |
| 6512281 | Method of forming a semiconductor device and an improved deposition system A method of forming a multi-layer structure over an insulating layer comprises the steps of: selectively depositing a barrier layer on a predetermined region of an insulating layer by use of a first deposition mask; selectively depositing a metal seed lay... | 01/28/2003 |
| 6511910 | Method for manufacturing semiconductor devices A semiconductor device includes a semiconductor substrate having a device element, an interlayer dielectric layer (silicon oxide layer, BPSG layer) formed on the semiconductor substrate, a through hole defined in the interlaver dielectric layer, a barrier... | 01/28/2003 |
