Class 257/E21.162 - On semiconductor body comprising Group IV element (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.161. This subclass
No. of patents: 272
Last issue date: 12/26/2006

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Number	Title	Issue Date
7153735	Method of manufacturing semiconductor device A method of manufacturing a semiconductor device comprises the steps of forming a first insulating film 9, 10 above a semiconductor substrate 1; forming a capacitor Q having a lower electrode 11a, a dielectric film 13a, and ...	12/26/2006
6699530	Method for constructing a film on a semiconductor wafer The construction of a film on a wafer, which is placed in a processing chamber, may be carried out through the following steps. A layer of material is deposited on the wafer. Next, the layer of material is annealed. Once the annealing is completed, the ma...	03/02/2004
6693335	Semiconductor raised source-drain structure A semiconductor structure which includes a raised source and a raised drain. The structure also includes a gate located between the source and drains. The gate defines a first gap between the gate and the source and a second gap between the gate and the d...	02/17/2004
6686636	Semiconductor raised source-drain structure A system comprising a memory device that includes at least one semiconductor structure wherein the semiconductor structure includes a raised source, a raised drain, a gate located between the source and the drain, a first capping layer in communication wi...	02/03/2004
6683355	Semiconductor raised source-drain structure A system comprising a memory device that includes at least one semiconductor structure wherein the semiconductor structure includes a raised source, a raised drain, a gate located between the source and the drain, a first capping layer in communication wi...	01/27/2004
6670682	Multilayered doped conductor A memory device addressing reliability and refresh characteristics through the use of a multilayered doped conductor, and a method making are disclosed. The multilayered doped conductor creates a high dopant concentration in the active area close to the c...	12/30/2003
6667523	Highly linear integrated resistive contact A semiconductor device or integrated circuit has high and low resistive contacts. Mobility spoiling ions such as carbon are implanted into all contacts of the substrate. High resistive contacts are temporarily covered with an oxide during processing to pr...	12/23/2003
6660604	Method of forming double junction region and method of forming transfer transistor using the same The present invention relates to a method of forming a dual junction region and a method of forming a transfer transistor using the same. A low-concentration junction region is formed. A high-concentration junction region is formed at a portion of the low...	12/09/2003
6653222	Plasma enhanced liner A method and structure for forming a refractory metal liner, includes depositing a layer of refractory metal on a first conductive layer, at least half of the depositing being carried out in the presence of an amount of passivating agent that is sufficien...	11/25/2003
6649539	Semiconductor contact fabrication method A method for reducing damage to a semiconductor structure resulting from migration of constituents of a first component part (3) of the structure into a subsequently deposited second component part (8) of the structure which makes contact with a surface o...	11/18/2003
6649478	Semiconductor device and method of manufacturing same A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconduc...	11/18/2003
6645831	Thermally stable crystalline defect-free germanium bonded to silicon and silicon dioxide A wafer pair comprising a substantially defect-free germanium wafer and methods of making the same. The wafer pair comprises the substantially defect-free germanium wafer directly bonded to a silicon wafer. The method of making the wafer pair comprises pl...	11/11/2003
6646320	Method of forming contact to poly-filled trench isolation region Existing polysilicon emitter technology is used to contact poly fill in a trench isolation structure. A standard single poly emitter window process is followed. An "emitter window" is masked directly over the polysilicon trench fill. Heavily doped single ...	11/11/2003
6620665	Method for fabricating semiconductor device A process control is performed for fabricating both a wafer for a device including a Ge-containing semiconductor film and a wafer for a device, for example, including no Ge-containing semiconductor film on a common fabrication line. When the wafer includi...	09/16/2003
6617242	Method for fabricating interlevel contacts of aluminum/refractory metal alloys A method for fabricating interlevel contacts in semiconductor integrated circuits provides for formation of a contact opening through an insulating layer. A layer of refractory metal, or refractory metal alloy, is deposited over the surface of the integra...	09/09/2003
6610582	Field-assisted fusion bonding A method of field-assisted fusion bonding produces multiple-layer devices. Contacts (301, 303, 305, 307, 309) are placed at various points along different surfaces of a combination of two or more wafers (201, 203, 205, 501, 503, 505, 801, 803). An electri...	08/26/2003
6596606	Semiconductor raised source-drain structure A method of forming a semiconductor structure which includes a raised source, a raised drain, a gate located between the source and the drain, a first capping layer in communication with at least a portion of the gate and the source, a second capping laye...	07/22/2003
6597045	Semiconductor raised source-drain structure A semiconductor structure which includes a raised source, a raised drain, a gate located between the source and the drain, a first capping layer in communication with at least a portion of the gate and the source, a second capping layer in communication w...	07/22/2003
6569766	Method for forming a silicide of metal with a high melting point in a semiconductor device A method for forming a silicide of a metal with high-melting-point in a semiconductor device includes the step of removing a higher-density impurity area which acts for prevention of forming the metal-silicide layer on the surface of the impurity-diffused...	05/27/2003
6562699	Process for manufacturing semiconductor device By removing halogen atoms existing on the surface of the silicon layer and in the subsurface thereof so that the concentration of halogen atoms becomes 100 ppm or lower and forming an electrode on the resulting silicon layer, the electrode which has a low...	05/13/2003
6559489	Semiconductor device and method of manufacturing the same A semiconductor device capable of a high-speed operation is provided. The semiconductor device is provided with low concentration impurity regions, a gate electrode formed with gate oxide film interposed between the gate electrode and a silicon substrate,...	05/06/2003
6548421	Method for forming a refractory-metal-silicide layer in a semiconductor device A method for forming a silicide of a metal with high-melting-point in a semiconductor device includes the step of removing a higher-density impurity area which acts for prevention of refractory-metal-silicification of diffused regions between the steps of...	04/15/2003
6548847	SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING A FIRST WIRING STRIP EXPOSED THROUGH A CONNECTING HOLE, A TRANSITION-METAL FILM IN THE CONNECTING HOLE AND AN ALUMINUM WIRING STRIP THEREOVER, AND A TRANSITION-METAL NITRIDE FILM BETWEEN THE ALUMINUM WIRING STRIP AND THE TRANSITION-METAL FILM Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating fi...	04/15/2003
6518618	Integrated memory cell and method of fabrication A nonvolatile memory cell comprising a pair of spaced apart shallow trench isolation regions formed in a substrate and defining a substrate active region. A tunnel dielectric is formed on the substrate active region. A floating gate is formed on the tunne...	02/11/2003
6509625	Guard structure for bipolar semiconductor device A guard ring structure formed around the periphery of a bipolar semiconductor device. A guard region (11) is formed in a substrate (1) of the device so as to extend adjacent a peripheral portion of the device. An insulating layer (3) is formed on the subs...	01/21/2003
6500742	Construction of a film on a semiconductor wafer The construction of a film on a wafer, which is placed in a processing chamber, may be carried out through the following steps. A layer of material is deposited on the wafer. Next, the layer of material is annealed. Once the annealing is completed, the ma...	12/31/2002
6498366	Semiconductor device that exhibits decreased contact resistance between substrate and drain electrode A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconduc...	12/24/2002
6482681	Hydrogen implant for buffer zone of punch-through non epi IGBT An IGBT is formed in a thin (less than 250 microns thick) float zone silicon wafer using a hydrogen implant to form an N+ buffer layer at the bottom of the wafer. A weak anode is formed on the bottom of the wafer. A single hydrogen implant, or ...	11/19/2002
6472328	Methods of forming an electrical contact to semiconductive material A method of forming an electrical contact to semiconductive material includes forming an insulative layer over a contact area of semiconductive material. A contact opening is etched through the insulative layer to the semiconductive material contact area....	10/29/2002
6455412	Semiconductor contact via structure and method A contact opening through an insulating layer is filled with metal and etched back to form a metal plug within the opening. A metal interconnect line can then be formed over the contact, and makes electrical contact with the metal plug. Since the contact ...	09/24/2002
6444036	Construction of a film on a semiconductor wafer The construction of a film on a wafer, which is placed in a processing chamber, may be carried out through the following steps. A layer of material is deposited on the wafer. Next, the layer of material is annealed. Once the annealing is completed, the ma...	09/03/2002
6440827	Method for fabricating a semiconductor component having a wiring which runs piecewise in the substrate, and also a semiconductor component which can be fabricated by this method A method for fabricating a wiring which runs at least piecewise in a substrate. At least one conductive connection runs in the semiconductor substrate and at least one conductive connection runs on the semiconductor substrate being provided. The semicondu...	08/27/2002
6403472	Method of forming resistive contacts on intergrated circuits with mobility spoiling ions including high resistive contacts and low resistivity silicide contacts A semiconductor device or integrated circuit has high and low resistive contacts. Mobility spoiling species such as carbon or oxygen are implanted into all contacts. The high resistive contacts are covered with a barrier metal to protect silicide from che...	06/11/2002
6373108	Semiconductor device having reduced sheet resistance of source/drain regions Source/drain diffusion regions are formed on the silicon substrate such that the source/drain diffusion regions sandwich a gate electrode from both sides on the silicon substrate. Sidewall oxide films are formed, one on each side surface of the gate elect...	04/16/2002
6365495	Method for performing metallo-organic chemical vapor deposition of titanium nitride at reduced temperature A process for chemical vapor deposition of titanium nitride film using thermal decomposition of a metal-organic compound is disclosed. In particular, the deposition of titanium nitride film from tetrakis dimethylamino-titanium (TDMAT) is performed at a te...	04/02/2002
6351016	Technology for high performance buried contact and tungsten polycide gate integration A buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. ...	02/26/2002
6342412	Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating fi...	01/29/2002
6335272	Buried butted contact and method for fabricating A buried butted contact and method for its fabrication are provided which includes a substrate having dopants of a first conductivity type and having shallow trench isolation. Dopants of a second conductivity type are located in the bottom of an opening i...	01/01/2002
6329274	Method of producing semiconductor device For forming electrical interlayer contact in a semiconductor device, an insulating film is formed on a first electrically conductive layer and then a contact hole is formed in the insulating film to expose a part of the first electroconductive, an activat...	12/11/2001
6306714	Method to form an elevated S/D CMOS device by contacting S/D through the contact of oxide A method of fabrication of an elevated source/drain (S/D) for a MOS device. A first insulating layer having a gate opening and source/drain openings is formed over a substrate. We form a LDD resist mask having opening over the source/drain openings over t...	10/23/2001

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Class 257/E21.162 - On semiconductor body comprising Group IV element (EPO)