Class 257/E21.158 - Manufacture of electrode on semiconductor body using process other than by epitaxial growth, diffusion of impurities, alloying of impurity materials, or radiation bombardment (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.085. This subclass
No. of patents: 234
Last issue date: 03/25/2008

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Number	Title	Issue Date
7348648	Interconnect structure with a barrier-redundancy feature An interconnect structure that includes a barrier-redundancy feature which is capable of avoiding a sudden open circuit after an electromigration (EM) failure as well as a method of forming the same are provided. In accordance with the present invention, the barrier...	03/25/2008
7344938	Method of fabricating memory A method of fabricating a memory device is described. During the process of forming the memory cell area and the periphery area of a semiconductor device a photoresist layer is formed on the memory cell area before the spacers are formed on the sidewalls of the gate...	03/18/2008
7326981	Methods and apparatuses for producing a polymer memory device Embodiments of the invention provide a method for producing ferroelectric polymer devices (FPMDs) employing conditions that avoid or reduce detrimental impact on the ferroelectric polymer film. For one embodiment, a damascene patterning metallization technique is us...	02/05/2008
7312138	Semiconductor device and method of manufacture thereof A method of manufacturing a MOS transistor incorporating a silicon oxide film serving as a gate insulating film and containing nitrogen and a polycrystalline silicon film serving as a gate electrode and containing a dopant and arranged such that the gate electrode i...	12/25/2007
7253104	Methods of forming particle-containing materials The invention includes methods of forming particle-containing materials, and also includes semiconductor constructions comprising particle-containing materials. One aspect of the invention includes a method in which a first monolayer is formed across at least a port...	08/07/2007
7232733	Method of forming an integrated circuit incorporating higher voltage devices and low voltage devices therein A method of forming an integrated circuit configured to accommodate higher voltage and low voltage devices. In one embodiment, the method of forming the integrated circuit includes forming a transistor by forming a gate over a semiconductor substrate. The method of ...	06/19/2007
7186634	Method for forming metal single-layer film, method for forming wiring, and method for producing field effect transistors A method for producing a field effect transistor having source/drain electrodes of metal single-layer film firmly adhering to the gate insulating film is provided. The method includes forming a gate electrode on a support, forming a gate insulating film on the suppo...	03/06/2007
7153722	Method and apparatus for manufacturing photovoltaic device A method of manufacturing a photovoltaic device includes: a step of fixing thin metal wires which are coated with electroconductive resin, to a principal surface of a photovoltaic member; a step of heating the photovoltaic member to which the thin metal wires are fi...	12/26/2006
7141456	Methods of fabricating Fin-field effect transistors (Fin-FETs) having protection layers Methods for fabricating Fin-Field Effect Transistors (Fin-FETs) are provided. A fin is formed on an integrated circuit substrate. The fin defines a trench on the integrated circuit substrate. A first insulation layer is formed in the trench such that a surface of th...	11/28/2006
7138281	Fabrication method of multisensors chips for detecting analytes A method includes (a) putting a multielectrodic chip lithographed in a wafer that contains between 2 and 2000 individually polarisable electrodes, in contact with a solution or suspension that includes modified colloidal particles with a (bio)chemical recognition el...	11/21/2006
7101780	Method for manufacturing Group-III nitride compound semiconductor device After a p-seat electrode-forming layer is laminated onto a light-transmissive electrode-forming layer, a first heating step and a second heating step are carried out for alloying the two layers. In the first heating step, heat treatment is performed at a relatively ...	09/05/2006
6784472	Semiconductor device and method for fabricating the same A semiconductor device comprises a first transistor 38a having a first gate electrode 22; a second transistor 38b having a second gate electrode 34 which is different from the first gate electrode; an insulation film 28	08/31/2004
6649478	Semiconductor device and method of manufacturing same A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconduc...	11/18/2003
6605519	Method for thin film lift-off processes using lateral extended etching masks and device A method for forming an etching mask structure on a substrate includes etching the substrate, laterally expanding the etching mask structure, and depositing a self-aligned metal layer that is aligned to the originally masked area. The etching can be isotr...	08/12/2003
6498366	Semiconductor device that exhibits decreased contact resistance between substrate and drain electrode A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconduc...	12/24/2002
6469389	Contact plug Within an integrated circuit, a contact plug with a height not extending above the level of the gate/wordline nitride is nonetheless provided with a relatively large contact area or landing pad, significantly larger than the source/drain region to which t...	10/22/2002
6303499	Process for preparing semiconductor device A process for preparing a semiconductor device includes a step of surface-modifying a desired portion of the surface of a substrate carried out in an atmosphere containing oxygen or nitrogen atoms. The process also includes a step of depositing selectivel...	10/16/2001
6285073	Contact structure and method of formation The horizontal surface area required to contact semiconductor devices, in integrated circuits fabricated with trench isolation, is minimized without degrading contact resistance by utilizing the vertical surface area of the trench sidewall. A trench isola...	09/04/2001
6284648	Semiconductor processing method of forming a buried contact A semiconductor processing method of forming a buried contact to a substrate region includes, a) providing a masking layer over a bulk semiconductor substrate; b) with the masking in place, exposing the substrate to oxidation conditions effective to grow ...	09/04/2001
6093963	Dual landing pad structure including dielectric pocket A dual landing pad structure is formed with a dielectric pocket. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is formed over the first dielectric layer and in the open...	07/25/2000
6066549	Semiconductor processing method of forming a conductive gate line and semiconductor processing method of making ohmic contact between a transistor gate line and a substrate diffusion region A semiconductor processing method of forming a conductive gate line includes forming a field oxide mask over a portion of a semiconductor substrate. Field oxide regions are formed adjacent the field oxide mask. A portion of the field oxide mask is removed...	05/23/2000
6040221	Semiconductor processing methods of forming a buried contact, a conductive line, an electrical connection to a buried contact area, and a field effect transistor gate A semiconductor processing method of forming a field effect transistor gate over a semiconductor substrate includes forming a gate dielectric layer over substrate active area while a buried contact mask to said active area is in place. A field effect tran...	03/21/2000
6034435	Metal contact structure in semiconductor device A structure of metal contact portion of a semiconductor device, includes a semiconductor substrate having an impurity doped junction therein, an insulating layer pattern formed on the semiconductor substrate having a contact hole through the insulating la...	03/07/2000
5994187	Method of manufacturing a vertical semiconductor device A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconduc...	11/30/1999
5958505	Layered structure with a silicide layer and process for producing such a layered structure A process for producing a layered structure in which a silicide layer on a silicon substrate is subjected to local oxidation to cause the boundary layer side of the silicide layer to grow into the silicon substrate....	09/28/1999
5942785	Poly plug to reduce buried contact series resistance An integrated circuit device having a reduced buried contact resistance is achieved. A gate electrode lies on the surface of a semiconductor substrate. Source/drain regions within the semiconductor substrate surround the gate electrode. A polysilicon cont...	08/24/1999
5858865	Method of forming contact plugs Within an integrated circuit, a contact plug with a height not extending above the level of the gate/wordline nitride is nonetheless provided with a relatively large contact area or landing pad, significantly larger than the source/drain region to which t...	01/12/1999
5858872	Metal contact structure in semiconductor device, and a method of forming the same A process of forming a metal contact portion of a semiconductor device and a structure thereof are disclosed. The process includes the steps of forming an insulating layer on a semiconductor substrate in which a doped junction has been formed, photo-etchi...	01/12/1999
5856067	Contact photolithographic process for realizing metal lines on a substrate by varying exposure energy The present invention concerns a contact photolithographic process for realizing submicrometer metal lines, in particular lines for devices such as FETs, MESFETs and ICs, with width different from the pattern width on the masks, through contact photolitho...	01/05/1999
5844284	Damage free buried contact using salicide technology A semiconductor cell with a buried contact uses highly selective etching techniques in combination with a thin oxide etching stop to prevent damage to the buried contact during the etching process. A cavity is formed in the oxide layer between the buried ...	12/01/1998
5723381	Formation of self-aligned overlapping bitline contacts with sacrificial polysilicon fill-in stud A method of forming a self-aligned overlapping bitline contact, includes steps of first depositing a sacrificial polysilicon on a spacer dielectric film, and thereafter patterning the polysilicon. The polysilicon film is a sacrificial fill-in for a bitlin...	03/03/1998
5702979	Method of forming a landing pad structure in an integrated circuit A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A ...	12/30/1997
5689130	Vertical semiconductor device with ground surface providing a reduced ON resistance A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconduc...	11/18/1997
5681778	Semiconductor processing method of forming a buried contact and conductive line A semiconductor processing method of forming a buried contact to a substrate region includes, a) providing a masking layer over a bulk semiconductor substrate; b) with the masking in place, exposing the substrate to oxidation conditions effective to grow ...	10/28/1997
5679607	Method of manufacturing a damage free buried contact using salicide technology A manufacturing process for a CMOS cell with a buried contact uses highly selective etching techniques in combination with a thin oxide etching stop to prevent damage to the buried contact during the etching process. A cavity is formed in the oxide layer ...	10/21/1997
5677249	Semiconductor apparatus and production method for the same A gate wire is formed so as to extend from an active area to a separation, and an impurity diffused area is formed on each side of the gate electrode located on the active area. A contact member for connecting the gate wire to a first layer aluminum inter...	10/14/1997
5668051	Method of forming poly plug to reduce buried contact series resistance A new method of forming improved buried contact junctions is described. A first layer of polysilicon is deposited overlying a gate silicon oxide layer on a semiconductor substrate. These layers are etched away to provide an opening to the semiconductor su...	09/16/1997
5663096	Method of manufacturing a vertical semiconductor device with ground surface providing a reduced ON resistance A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconduc...	09/02/1997
5658826	Method for fabricating semiconductor device Method for fabricating a semiconductor device is disclosed, including the steps of: forming a first resist layer on a substrate; patterning a predetermined region of the first resist layer to form a pattern having a first width which exposes the substrate...	08/19/1997
5654231	Method of eliminating buried contact trench in SRAM technology A new method of forming an improved buried contact junction is described. A first polysilicon layer is deposited overlying a gate silicon oxide layer on the surface of a semiconductor substrate. The first polysilicon and gate oxide layers are etched away ...	08/05/1997

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Class 257/E21.158 - Manufacture of electrode on semiconductor body using process other than by epitaxial growth, diffusion of impurities, alloying of impurity materials, or radiation bombardment (EPO)