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| Number | Title | Issue Date |
| 7435628 | Method of forming a vertical MOS transistor A vertical MOS transistor has a source region, a channel region, and a drain region that are vertically stacked, and a trench that extends from the top surface of the drain region through the drain region, the channel region, and partially into the source region. Th... | 10/14/2008 |
| 7432164 | Semiconductor device comprising a transistor having a counter-doped channel region and method for forming the same A method for making a semiconductor device includes providing a first substrate region and a second substrate region, wherein at least a part of the first substrate region has a first conductivity type and at least a part of the second substrate region has a second ... | 10/07/2008 |
| 7335586 | Sealing porous dielectric material using plasma-induced surface polymerization A method for sealing a porous dielectric layer atop a substrate, wherein the dielectric layer is patterned to form at least a trench and at least a via, comprises applying a first plasma to a surface of the dielectric layer to silanolize the surface, treating the su... | 02/26/2008 |
| 7329956 | Dual damascene cleaning method A semiconductor structure having a pore sealed portion of a dielectric layer is provided. Exposed pores of the dielectric material are sealed using an anisotropic plasma so that pores along the bottom of the opening are sealed, and pores along sidewalls of the openi... | 02/12/2008 |
| 7323369 | Fabrication method for thin film transistor array substrate Scan lines are formed on a substrate. A patterned dielectric layer and a patterned semiconductor layer are formed to cover portions of the scan lines. A patterned transparent conductive layer and a patterned metal layer are sequentially formed to define data lines, ... | 01/29/2008 |
| 7309620 | Use of sacrificial layers in the manufacture of high performance systems on tailored substrates The invention relates to methods for preparing a removable system on a mother substrate. The method deposits a high surface to volume sacrificial layer on a mother substrate and stabilizes the sacrificial layer by a) removing volatile chemical species in and on the ... | 12/18/2007 |
| 7306998 | Formation of abrupt junctions in devices by using silicide growth dopant snowplow effect A method of forming an abrupt junction device with a semiconductor substrate is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed on the gate dielectric. A sidewall spacer is formed on the semiconductor substrate adjacent the g... | 12/11/2007 |
| 7303967 | Method for fabricating transistor of semiconductor device Disclosed is a method for fabricating a transistor of a semiconductor device, the method comprising the steps of: providing a semiconductor; forming a gate electrode; performing a low-density ion implantation process with respect to the substrate, thereby forming an... | 12/04/2007 |
| 7300826 | Manufacturing method of semiconductor and manufacturing method of semiconductor device The nickel element is provided selectively, i.e., adjacent to part of the surface of an amorphous silicon film in a long and narrow opening. The amorphous silicon film is irradiated with linear infrared light beams emitted from respective linear infrared lamps while... | 11/27/2007 |
| 7235424 | Method and apparatus for enhanced CMP planarization using surrounded dummy design In one embodiment, the disclosure relates to a method and apparatus for inserting dummy patterns in sparsely populated portions of a metal layer. The dummy pattern counters the effects of variations of pattern density in a semiconductor layout which can cause uneven... | 06/26/2007 |
| 7214988 | Metal oxide semiconductor transistor A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a ... | 05/08/2007 |
| 6700175 | Vertical semiconductor device having alternating conductivity semiconductor regions There is provided a method of manufacturing a vertical semiconductor device including a structural section in which an n- -type semiconductor region and a p- -type semiconductor region are arranged alternately without filling trenche... | 03/02/2004 |
| 6696335 | Method for forming a diffusion region For particularly simple and targeted formations of a diffusion region, an interfacial region of a semiconductor substrate is subjected to a thermal transformation process and thereby carry out the thermally activated diffusion of a dopant in a substantial... | 02/24/2004 |
| 6670682 | Multilayered doped conductor A memory device addressing reliability and refresh characteristics through the use of a multilayered doped conductor, and a method making are disclosed. The multilayered doped conductor creates a high dopant concentration in the active area close to the c... | 12/30/2003 |
| 6660571 | High voltage power MOSFET having low on-resistance A power MOSFET is provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. First and second body regions are located in the epitaxial layer and define a drift re... | 12/09/2003 |
| 6656799 | Method for producing FET with source/drain region occupies a reduced area A semiconductor device having a device separation region and an active region includes a gate oxide film, a source/drain region, and an electrode which is electrically coupled to the source/drain region. The active region is in contact with the gate oxide... | 12/02/2003 |
| 6646320 | Method of forming contact to poly-filled trench isolation region Existing polysilicon emitter technology is used to contact poly fill in a trench isolation structure. A standard single poly emitter window process is followed. An "emitter window" is masked directly over the polysilicon trench fill. Heavily doped single ... | 11/11/2003 |
| 6633070 | Semiconductor device A field-effect transistor including a gate electrode, silicon layers, and source and drain regions at a surface of a silicon substrate. Sidewall insulating films on the opposite side surfaces of the gate electrode are located between the gate electrode an... | 10/14/2003 |
| 6627949 | High voltage power MOSFET having low on-resistance A power MOSFET is provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. First and second body regions are located in the epitaxial layer and define a drift re... | 09/30/2003 |
| 6627502 | Method for forming high concentration shallow junctions for short channel MOSFETs A method is taught for forming shallow LDD diffusions using polysilicon sidewalls as a diffusion source. The polysilicon sidewalls are formed along side squared-off silicon nitride sidewall spacers which have an essentially rectangular cross section and a... | 09/30/2003 |
| 6541317 | Polysilicon doped transistor Steep concentration gradients are achieved in semiconductor device of small sizes by using implanted polycrystalline material such as polysilicon as a solid diffusion source. Rapid diffusion of impurities along grain boundaries relative to diffusion rates... | 04/01/2003 |
| 6515340 | Semiconductor device A semiconductor device having a device separation region and an active region includes a gate oxide film, a source/drain region, and an electrode which is electrically coupled to the source/drain region. The active region is in contact with the gate oxide... | 02/04/2003 |
| 6504217 | Semiconductor device and a method of manufacturing the same A low-concentration impurity region and a high-concentration impurity region are formed respectively near the lower surface and the upper surface of an undoped polysilicon film by a first and second ion-implanations. A refractory metal film of tungsten or... | 01/07/2003 |
| 6342441 | Method for fabricating semiconductor device A method for fabricating a semiconductor substrate includes forming a silicide layer at a predetermined portion of a semiconductor substrate, implanting two or more impurity ions before annealing, and forming an impurity region in the semiconductor substr... | 01/29/2002 |
| 6326664 | Transistor with ultra shallow tip and method of fabrication A novel transistor with a low resistance ultra shallow tip region and its method of fabrication. The novel transistor of the present invention has a source/drain extension or tip comprising an ultra shallow region which extends beneath the gate electrode ... | 12/04/2001 |
| 6323525 | MISFET semiconductor device having relative impurity concentration levels between layers A semiconductor device having a MISFET with an EV source/drain structure has a gate electrode formed on part of a first p-type semiconductor layer via a gate insulating film. A second n+ -type semiconductor layer is formed in the prospective so... | 11/27/2001 |
| 6309935 | Methods of forming field effect transistors Methods of forming field effect transistors. In one aspect, a method of forming a field effect transistor includes: a) providing a gate structure over a semiconductor substrate, the gate structure comprising a conductively-doped polysilicon region and a d... | 10/30/2001 |
| 6303449 | Method to form self-aligned elevated source/drain by selective removal of gate dielectric in the source/drain region followed by poly deposition and CMP A method of manufacturing a self aligned elevated source/drain (S/D). A first insulating layer is formed over a substrate. The first insulating layer having at least a gate opening and source/drain (S/D) openings adjacent to the gate opening. Spacer porti... | 10/16/2001 |
| 6291861 | Semiconductor device and method for producing the same A semiconductor device having a device separation region and an active region includes a gate oxide film, a source/drain region, and an electrode which is electrically coupled to the source/drain region. The active region is in contact with the gate oxide... | 09/18/2001 |
| 6287953 | Minimizing transistor size in integrated circuits A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal space between gate and the local interconnects by fabricating the source and drain of the FET and the ... | 09/11/2001 |
| 6284609 | Method to fabricate a MOSFET using selective epitaxial growth to form lightly doped source/drain regions A new method of fabricating a sub-quarter micron MOSFET device is achieved. A semiconductor substrate is provided. Isolation regions are formed in this substrate. An oxide layer is provided overlying both the substrate and the isolation regions. The oxide... | 09/04/2001 |
| 6258661 | Formation of out-diffused bitline by laser anneal The present invention provides methods of forming an out-diffused bitline in a semiconductor substrate by utilizing a laser annealing step wherein the dopant material in the trench region is out-diffused into the semiconductor substrate. The out-diffused ... | 07/10/2001 |
| 6238986 | Formation of junctions by diffusion from a doped film at silicidation High integrity shallow source/drain junctions are formed employing cobalt silicide contacts. A layer of cobalt and a cap layer of titanium or titanium nitride are deposited on a substrate above intended source/drain regions, followed by silicidation. Embo... | 05/29/2001 |
| 6207493 | Formation of out-diffused bitline by laser anneal The present invention provides methods of forming an out-diffused bitline in a semiconductor substrate by utilizing a laser annealing step wherein the dopant material in the trench region is out-diffused into the semiconductor substrate. The out-diffused ... | 03/27/2001 |
| 6198143 | Semiconductor device including a layer of thermally stable titanium silicide Highly refractory titanium silicide structure comprises a titanium silicide film formed on a silicon crystal surface and a thermal oxide film formed on this titanium silicide film. A manufacturing method of the highly refractory titanium silicide is as fo... | 03/06/2001 |
| 6180988 | Self-aligned silicided MOSFETS with a graded S/D junction and gate-side air-gap structure A MOSFET includes a gate oxide formed on a substrate. A thin dielectric layer is formed on the side walls of the gate. A gate is formed on the gate oxide. A first metal silicide layer is formed on top of the gate to increase the conductivity of the gate. ... | 01/30/2001 |
| 6165826 | Transistor with low resistance tip and method of fabrication in a CMOS process A novel transistor with a low resistance ultra shallow tip region and its method of fabrication in a complementary metal oxide semiconductor (CMOS) process. According to the preferred method of the present invention, a first gate dielectric and a first ga... | 12/26/2000 |
| 6150243 | Shallow junction formation by out-diffusion from a doped dielectric layer through a salicide layer Self-aligned, ultra-shallow, heavily-doped source and drain regions of a MOS device are formed by implanting dopant containing ions in a dielectric layer formed on metal silicide layer portions on regions of a silicon-containing substrate where source and... | 11/21/2000 |
| 6146954 | Minimizing transistor size in integrated circuits A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal insulating space between polysilicon gate and the local interconnects by fabricating the source and dr... | 11/14/2000 |
| 6136673 | Process utilizing selective TED effect when forming devices with shallow junctions A process for device fabrication in which transient enhanced diffusion (TED) is used to obtain a desired distribution of dopants in a crystalline substrate is disclosed. In the process, at least two dopants and a non-dopant are introduced into the same re... | 10/24/2000 |
