Class 257/E21.038 - Characterized by process involved to create mask, e.g., lift-off mask, sidewalls, or to modify mask, such as pre-treatment, post-treatment (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.036. This subclass
No. of patents: 268
Last issue date: 10/07/2008

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Number	Title	Issue Date
7432194	Etching method and method for forming contact opening An etching method is described, including a first etching step and a second etching step. The temperature of the second etching step is higher than that of the first etching step, such that the after-etching-inspection (AEI) critical dimension is smaller than the af...	10/07/2008
7419845	Methods of making electromechanical three-trace junction devices Methods of producing an electromechanical circuit element are described. A lower structure having lower support structures and a lower electrically conductive element is provided. A nanotube ribbon (or other electromechanically responsive element) is formed on an up...	09/02/2008
7396781	Method and apparatus for adjusting feature size and position Variations in the pitch of features formed using pitch multiplication are minimized by separately forming at least two sets of spacers. Mandrels are formed and the positions of their sidewalls are measured. A first set of spacers is formed on the sideswalls. The cri...	07/08/2008
7351666	Layout and process to contact sub-lithographic structures An integrated circuit and method for fabrication includes first and second structures, each including a set of sub-lithographic lines, and contact landing segments connected to at least one of the sub-lithographic lines at an end portion. The first and second struct...	04/01/2008
7307306	Etch mask and method of forming a magnetic random access memory structure A method for forming an MRAM bit is described that includes providing a covering layer over an integrated circuit structure. In one embodiment, the covering layer includes tantalum. A first mask layer is formed over the covering layer followed by a second mask layer...	12/11/2007
7271098	Method of fabricating a desired pattern of electronically functional material Provided is a method forming a desired pattern of electronically functional material 3 on a substrate 1. The method comprises the steps of: creating a first layer of patterning material 2 on the substrate whilst leaving areas of the substrate ex...	09/18/2007
7265013	Sidewall image transfer (SIT) technologies A structure fabrication method. The method comprises providing a structure which comprises (a) a to-be-etched layer, (b) a memory region, (c) a positioning region, (d) and a capping region on top of one another. Then, the positioning region is indented. Then, a conf...	09/04/2007
7241688	Aperture masks for circuit fabrication Aperture masks and deposition techniques for using aperture masks are described. In addition, techniques for creating aperture masks and other techniques for using the aperture masks are described. The various techniques can be particularly useful in creating circui...	07/10/2007
7205244	Patterning substrates employing multi-film layers defining etch-differential interfaces The present invention features a method of patterning a substrate that includes forming, on the substrate, a multi-layer film with a surface, an etch rate interface and an etch-differential interface. The etch-differential interface is defined between the etch rate ...	04/17/2007
7163879	Hard mask etch for gate polyetch A transistor gate structure that is free from notches is formed by using a hard mask. The hard mask has a bilayer structure of a BARC (bottom antireflective coating) over a silicon dioxide layer. A photoresist layer is formed over a portion corresponding to the gate...	01/16/2007
7071126	Densifying a relatively porous material An interlayer dielectric may be exposed to a gas cluster ion beam to densify an upper layer of the interlayer dielectric. As a result, the upper layer of the interlayer dielectric may be densified without separate deposition steps and without the need for etch stops...	07/04/2006
6703304	Dual damascene process using self-assembled monolayer and spacers A method of fabricating a trench on an integrated circuit having first and second insulative layers includes providing a layer of material over the insulative layers; forming a first self-assembled monolayer on the layer of material; etching the first sel...	03/09/2004
6696363	Method of and apparatus for substrate pre-treatment The present invention relates generally to a method and apparatus for converting a precursor material, preferably organometallic, to a film, preferably metal-containing, that is adherent to at least a portion of a substrate. Both method and apparatus incl...	02/24/2004
6682657	Three dimensional etching process A method of forming three-dimensional structures on a substrate by a single reactive ion each run whereby a mask is formed on said substrate before a series of iterations are carried out, each iteration including a mask etch and a substrate etch, so that ...	01/27/2004
6682988	Growth of photoresist layer in photolithographic process A method of fabricating a feature of an integrated circuit in a layer of material includes providing a layer of photoresist having a first thickness over the layer of material; forming apertures in the layer of photoresist; growing the layer of photoresis...	01/27/2004
6673714	Method of fabricating a sub-lithographic sized via A method of fabricating a sub-lithographic sized via is disclosed. A dual-polymer method is used to form a stacked layer of polymer materials wherein a first polymer layer has a first etch rate and a second polymer layer has a second etch rate. The first ...	01/06/2004
6669995	Method of treating an anti-reflective coating on a substrate A method of treating an anti-reflective coating on a substrate. The method includes exposing the anti-reflective coating to a dosage of ultraviolet radiation sufficient to result in the direct removal of at least a portion of the exposed anti-reflective c...	12/30/2003
6670277	Method of manufacturing semiconductor device A semiconductor device manufacturing method for manufacturing a semiconductor device of constant finished dimensions as designed even when a material which is difficult to increase etch selectivity to a silicon film in a gate electrode or wiring structure...	12/30/2003
6667237	Method and apparatus for patterning fine dimensions A process of forming fine repetitive geometries using a mask having large mask dimensions. The pitch of the masking pattern on the mask is divided by the process to obtain a smaller pitch in the fine repetitive geometries. At least two working materials a...	12/23/2003
6664191	Non self-aligned shallow trench isolation process with disposable space to define sub-lithographic poly space A method is provided of forming lines with spaces between memory cells below a minimum printing dimension of a photolithographic tool set. In one aspect of the invention, lines and spaces are formed in a first polysilicon layer that forms floating gates o...	12/16/2003
6653058	Methods for reducing profile variation in photoresist trimming A method of removing photoresist material from a semiconductor substrate includes providing a semiconductor substrate having a patterned photoresist mask. A layer comprised of polymer material is formed over the patterned photoresist mask. The layer compr...	11/25/2003
6642152	Method for ultra thin resist linewidth reduction using implantation The present invention relates to a system and a method for reducing the linewidth of ultra thin resist features. The present invention accomplishes this end by applying a densification process to an ultra thin resist having a thickness of less than about ...	11/04/2003
6638441	Method for pitch reduction A method for pitch reduction is disclosed. The method can form a pattern with a pitch 1/3 the original pitch formed by available photolithography technologies by only using one photo mask or one pattern transfer process, self-aligned etching back processe...	10/28/2003
6630720	Asymmetric semiconductor device having dual work function gate and method of fabrication An asymmetric semiconductor device and a method of making a pair of the asymmetric devices. The semiconductor device includes a layer of semiconductor material having a source and a drain, and a dual work function gate disposed on the layer of semiconduct...	10/07/2003
6620715	Method for forming sub-critical dimension structures in an integrated circuit A method is provided for fabricating a device, which includes device components and spacings that may each have a final dimension that is smaller than a minimum dimension obtainable by a photolithography process used to form the device components. In part...	09/16/2003
6617085	Wet etch reduction of gate widths A method of forming sublithography gate lengths involves the steps of patterning the layer of resist above the gate stack (including a gate layer, hardmask layer and etch-control layer) to a desired gate length and etching the etch-control layer and the h...	09/09/2003
6610607	Method to define and tailor process limited lithographic features using a modified hard mask process A method to define and tailor process limited lithographic features is provided. The method may be used to form sub lithographic spaces between features on a semiconductor wafer. A mask is formed and patterned on the wafer. Spacers are formed on sidewalls...	08/26/2003
6605541	Pitch reduction using a set of offset masks A method of manufacturing a semiconductor device having features with a dimension of 1/2the minimum pitch wherein the minimum pitch is determined by the parameters of the manufacturing process being used to manufacture the semiconductor device. A target l...	08/12/2003
6590250	DRAM capacitor array and integrated device array of substantially identically shaped devices Semiconductor processing methods include forming a plurality of patterned device outlines over a semiconductor substrate, forming electrically insulative partitions or spacers on at least a portion of the patterned device outlines, and forming a plurality...	07/08/2003
6570220	Fabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definition The invention relates to a method of forming reduced feature size spacers. The method includes providing a semiconductor substrate having an area region; patterning a first spacer over a portion of the area region of the substrate, the first spacer having...	05/27/2003
6566280	Forming polymer features on a substrate Polymer features may be formed on a substrate by applying a polymer to a photoresist pattern which is subsequently removed to generate the desired polymer features....	05/20/2003
6559002	Rough oxide hard mask for DT surface area enhancement for DT DRAM In a process for making a DT DRAM structure, the improvement of providing a surface area enhanced DT below the collar region and node capacitance that does not shrink with decreasing groundrule/cell size, comprising: a) providing a semiconductor substrate havi...	05/06/2003
6548423	Multilayer anti-reflective coating process for integrated circuit fabrication A method utilizing a multilayer anti-reflective coating layer structure. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be u...	04/15/2003
6548385	Method for reducing pitch between conductive features, and structure formed using the method A method is described which may be used to reduce a pitch between conductive features. One embodiment of the method involves forming a structure including a substrate, a conductive layer on the substrate, multiple photoresist features arranged on the cond...	04/15/2003
6541360	Bi-layer trim etch process to form integrated circuit gate structures A bi-layer trim etch process to form integrated circuit gate structures can include depositing an organic underlayer over a layer of polysilicon, depositing an imaging layer over the organic underlayer, patterning the imaging layer, selectively trim etchi...	04/01/2003
6541387	Process for implementation of a hardmask A resist layer is deposited atop a substrate and is patterned to expose portions of a substrate. A hardmask layer is deposited atop the patterned resist layer and atop the exposed portions of the substrate. The patterned resist layer is removed so that on...	04/01/2003
6528369	Layer structure having contact hole and method of producing same A dynamic random access memory (DRAM) device includes a stacked capacitor including a storage electrode, a dielectric film and a cell plate. In a preferred embodiment, the storage electrode contacts with a diffusion region of a substrate through a contact...	03/04/2003
6489237	Method of patterning lines in semiconductor devices A new process is provided for the creation of sub-micron conductive lines and patterns. A conductive layer is deposited over the surface of a substrate, a sacrificial layer that differs with the conductive layer in etch characteristics is deposited over t...	12/03/2002
6479861	Method for forming an etch mask during the manufacture of a semiconductor device A method used during the formation of a semiconductor device comprises the steps of forming a polycrystalline silicon layer over a semiconductor substrate assembly and forming a silicon nitride layer over the polycrystalline silicon layer. A silicon dioxi...	11/12/2002
6475867	Method of forming integrated circuit features by oxidation of titanium hard mask An exemplary method of forming integrated circuit device features by oxidization of titanium hard mask is described. This method can include providing a photoresist pattern of photoresist features over a first layer of material deposited over a second lay...	11/05/2002

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Class 257/E21.038 - Characterized by process involved to create mask, e.g., lift-off mask, sidewalls, or to modify mask, such as pre-treatment, post-treatment (EPO)