Class 257/E21.036 - Characterized by their size, orientation, disposition, behavior, shape, in horizontal or vertical plane (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E21.033. This subclass
No. of patents: 61
Last issue date: 09/16/2008

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Number	Title	Issue Date
7425483	Structure and method of fabricating a hybrid substrate for high-performance hybrid-orientation silicon-on-insulator CMOS devices The present invention provides a method of integrating semiconductor devices such that different types of devices are formed upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. Specifically, the present inv...	09/16/2008
7381654	Method for fabricating right-angle holes in a substrate A method is disclosed for forming right-angle contact/via holes for semiconductor devices. A device is provided on a substrate and covered with a first dielectric layer. A second dielectric layer having an etch rate different from that of the first layer is provided...	06/03/2008
7355200	Ion-sensitive field effect transistor and method for producing an ion-sensitive field effect transistor An ion-sensitive field effect transistor has a gate consisting of metal silicate. The gate of metal silicate provides high resistance to aggressive measured substances and further has a high long-term stability. The gate of the ion-sensitive field effect transistor ...	04/08/2008
7329588	Forming a reticle for extreme ultraviolet radiation and structures formed thereby Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a plurality of openings in a portion of a first side of a substrate, bonding a first silicon layer of a silicon on insulator wafer to the first side of the sub...	02/12/2008
7304323	Test mask structure Disclosed is a test mask structure. The test mask structure of the present invention comprises at least an array pattern region, in a certain proportion to the final product, having a first pattern density according to the certain proportion; and at least one test m...	12/04/2007
7276793	Semiconductor device and semiconductor module A semiconductor device is provided wherein conductive paths 40, formed of crystal that grows better along the X-Y axis than along the Z axis, are embedded in an insulating resin 44, and the back surface of the conductive path 40 is exposed throu...	10/02/2007
7276453	Methods for forming an undercut region and electronic devices incorporating the same An electronic device having a substrate structure having an undercut region is provided and further included is a method for forming an undercut region of a substrate structure. The method includes forming a patterned protective layer over a first electrode. The met...	10/02/2007
7220612	Liquid crystal display device and fabricating method thereof A thin film transistor substrate and a fabricating method thereof for simplifying a process are disclosed. In a liquid crystal display device according to the present invention, a gate line is provided on a substrate. A data line crosses the gate line with having a ...	05/22/2007
7196005	Dual damascene process with dummy features A method for creating a hole in a semiconductor wafer includes forming a hard mask over a dielectric layer, the hard mask including a solid portion and a first opening. A patterning layer is provided over the hard mask, the patterning layer including second and thir...	03/27/2007
6632741	Self-trimming method on looped patterns A method of self-trimming pattern, includes forming a pattern containing a plurality of regular or irregular features within a first material deposited on a substrate, depositing a conformal layer of second material, and etching the second material to for...	10/14/2003
6544905	Metal gate trim process by using self assembled monolayers In a method of forming a metal gate of a semiconductor device, a substrate is provided, which includes a substrate body covered by a dielectric layer. A metal body having top and side surface is provided on the dielectric layer. A self-assembled monolayer...	04/08/2003
6458494	Etching method Etching method applicable to a semiconductor device fabrication and an MEMS(Micro-Electro-Mechanical System) process, including the steps of forming an etching mask on a substrate, forming a plurality of patterns in the etching mask corresponding to depth...	10/01/2002
6350623	Method of forming intermediate structures in porous substrates in which electrical and optical microdevices are fabricated and intermediate structures formed by the same The invention is a method of fabricating electrically passive components or optical elements on top or underneath of an integrated circuit by using a porous substrate that is locally filled with electrically conducting, light emitting, insulating or optic...	02/26/2002
6270685	Method for producing a semiconductor In a method for producing a semiconductor dynamic sensor, an anisotropic etching mask is formed on a (100) crystal orientation silicon substrate with a main portion and form-compensation portions formed at the corners of the main portion. Each of the form...	08/07/2001
6184151	Method for forming cornered images on a substrate and photomask formed thereby A method for forming square shape images in a lithographic process is disclosed wherein a first plurality of lines running in a first direction is defined in a first, usually sacrificial, layer, and then a second resist is defined wherein the lines run in...	02/06/2001
6168982	Manufacture of electronic devices comprising thin-film circuit elements The manufacture of AMLCDs and similar large-area electronic devices includes forming thin-film circuit elements (11, 12, 13, 14) on a substrate (10), with some of the process steps being self-aligned by shadow-masking. An upstanding post (20) is provided ...	01/02/2001
6130010	Method for producing a semiconductor dynamic sensor using an anisotropic etching mask In a method for producing a semiconductor dynamic sensor, an anisotropic etching mask is formed on a (100) crystal orientation silicon substrate with a main portion and form-compensation portions formed at the corners of the main portion. Each of the form...	10/10/2000
6027842	Process for controlling etching parameters Focus and exposure parameters may be controlled in a lithographic process for manufacturing microelectronics by creating a complementary tone pattern of shapes and spaces in a resist film on a substrate. Corresponding dimensions of the resist shape and sp...	02/22/2000
6013136	Apparatus for plasma-supported back etching of a semiconductor wafer A method for the manufacture of highly-integrated circuits on a semiconductor substrate includes applying coatings to front and back sides of a wafer of semiconductor material in at least one deposition process, and subsequently removing the coating on th...	01/11/2000
5976740	Process for controlling exposure dose or focus parameters using tone reversing pattern Focus and exposure parameters may be controlled in a lithographic process for manufacturing microelectronics by creating a complementary tone pattern of shapes and spaces in a resist film on a substrate. Corresponding dimensions of the resist shape and sp...	11/02/1999
5959325	Method for forming cornered images on a substrate and photomask formed thereby A method for forming square shape images in a lithographic process is disclosed wherein a first plurality of lines running in a first direction is defined in a first, usually sacrificial, layer, and then a second resist is defined wherein the lines run in...	09/28/1999
5943571	Method for manufacturing fine structures For manufacturing fine structures, nuclei that define the dimensions of the fine structures are formed on the surface of a substrate in a CVD process upon employment of a first process gas that contains SiH4 and GeH4 in a carrier gas...	08/24/1999
5846609	Masking methods for semiconductor materials A method of forming a mask including providing a fluid from a group including oxygen based, nitrogen based, or carbon based fluids, introducing a substrate of semiconductor material into the fluid, and growing a film with thickness in a range of 10-20 Å ...	12/08/1998
5811222	Method of selectively exposing a material using a photosensitive layer and multiple image patterns A method of selectively exposing a material over a substrate is disclosed. The method includes forming a material over a semiconductor substrate, forming a photosensitive layer over the material, projecting a first image pattern onto the photosensitive la...	09/22/1998
5795830	Reducing pitch with continuously adjustable line and space dimensions A method of forming sub-lithographic elements and spaces therebetween where the pitch may be reduced with continuously adjustable line and space dimensions, and a structure resulting from the method, are disclosed. A plurality of spaced convertible member...	08/18/1998
5766803	Mask generation technique for producing an integrated circuit with optimal metal interconnect layout for achieving global planarization A photolithography mask derivation process is provided for improving the overall planarity of interlevel dielectric deposited upon conductors formed by the derived photolithography mask. The photolithography mask is derived such that non-operational condu...	06/16/1998
5730798	Masking methods during semiconductor device fabrication A method of masking semiconductor substrates during fabrication of semiconductor devices includes positioning an oxide mask on the substrate so as to define a growth area and an unmasked portion the surface. A dense oxide layer is grown on the unmasked po...	03/24/1998
5439847	Integrated circuit fabrication with a raised feature as mask A method for etching metal conductors and stacks of conductors is disclosed. A doped silicon dioxide layer is deposited upon a metal or stack of conductive layers to be etched. A silicon dioxide layer is doped with phosphorous. Next, the silicon dioxide l...	08/08/1995
5298444	Method for manufacturing a field effect transistor A method for manufacturing a field effect transistor which includes one more spacer provided in the gate recess adjacent the drain sidewall than adjacent the source sidewall in the contact such that a gate metallization is displaced asymmetrically toward ...	03/29/1994
5278105	Semiconductor device with dummy features in active layers A design and method for fabricating devices with reduced loading effect is described. The disclosed design creates dummy features to increase the percentage of material remaining after etch of an active layer. This improves device reliability by preventin...	01/11/1994
4927772	Method of making high breakdown voltage semiconductor device A semiconductor device having at least one P-N junction and a multiple-zone junction termination extension (JTE) region which uniformly merges with the reverse blocking junction is disclosed. The blocking junction is graded into multiple zones of lower co...	05/22/1990
4830971	Method for manufacturing a semiconductor device utilizing self-aligned contact regions A method for manufacturing a semiconductor device of the invention comprises the steps of (a) forming a gate insulating film on a surface of a silicon substrate, and a gate electrode on said gate insulating film; (b) forming a source region and a drain region ...	05/16/1989
4820656	Method for producing a p-doped semiconductor region in an n-conductive semiconductor body A method for producing a p-doped semiconductor region in an n-conductive semiconductor body by means of diffusion using a combination of both aluminum and boron as dopants. The semiconductor body is positioned within a hollow silicon member which itself i...	04/11/1989
4797371	Method for forming an impurity region in semiconductor devices by out-diffusion The invention discloses a method including the following processes (a) through (c) for forming impurity regions in a semiconductor device (a) a process that forms at least one second conductive type impurity-doped region by doping second conductive type i...	01/10/1989
4758528	Self-aligned metal process for integrated circuit metallization A method of forming on a substrate a pattern of structures having a thickness on the order of one micron or less. A first insulating layer is formed on a major surface of a substrate, for example, a silicon body. A polycrystalline silicon layer is formed ...	07/19/1988
4757031	Method for the manufacture of a pn-junction having high dielectric strength A method for the manufacture of a pn-junction having high dielectric strength starting with a doped semiconductor body of a first conductivity type. A zone of a second conductivity type is formed in the semiconductor body inwardly from a surface thereof. ...	07/12/1988
4732869	Method of forming implanted regions in a semiconductor device by use of a three layer masking structure A method is provided in which an implantation treatment is carried out at a high energy of implantation in a semiconductor body (1) provided with a pattern of field insulation (6a) and in which the semiconductor body is provided with a masking, comprising...	03/22/1988
4691219	Self-aligned polysilicon base contact structure An integrated bipolar transistor having a self-aligned polysilicon base contact is formed by depositing a first doped polysilicon layer and a silicon nitride passivating layer on the surface of a semiconductor substrate having an isolated collector region...	09/01/1987
4672738	Method for the manufacture of a pn junction with high breakdown voltage A method for the manufacture of a pn junction having a high breakdown voltage at the boundary surface of a semiconductor body, utilizing a mask which has a relatively large opening for introducing a dopant therethrough into the semiconductor body, the mas...	06/16/1987
4670092	Method of fabricating a cantilever beam for a monolithic accelerometer A monolithic accelerometer is fabricated with an integral cantilever beam sensing element which is etched out of a silicon wafer from the back surface. A thermal silicon oxide is formed on both surfaces of a (100) silicon wafer. Silicon oxide is removed f...	06/02/1987

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Class 257/E21.036 - Characterized by their size, orientation, disposition, behavior, shape, in horizontal or vertical plane (EPO)