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Actor Marlon Brando has four patents, all named "Drumhead tensioning device and method."
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| Number | Title | Issue Date |
| 7439196 | Method for manufacturing pattern formed structure The main object of the present invention is to provide a method for manufacturing efficiently a pattern formed structure which has a surface having a property-varied pattern and can be used to manufacture a color filter or the like. In order to achieve the ob... | 10/21/2008 |
| 7381654 | Method for fabricating right-angle holes in a substrate A method is disclosed for forming right-angle contact/via holes for semiconductor devices. A device is provided on a substrate and covered with a first dielectric layer. A second dielectric layer having an etch rate different from that of the first layer is provided... | 06/03/2008 |
| 7378738 | Method for producing self-aligned mask, articles produced by same and composition for same A method for forming a self-aligned pattern on an existing pattern on a substrate comprising applying a coating of a solution containing a masking material in a carrier, the masking material being either photo or thermally sensitive; performing a blanket exposure of... | 05/27/2008 |
| 7368390 | Photolithographic patterning process using a carbon hard mask layer of diamond-like hardness produced by a plasma-enhanced deposition process A carbon hard mask layer is applied to a substrate to be patterned by means of a plasma-enhanced deposition process in such a manner that it has a hardness comparable to that of diamond in at least one layer thickness section. During the production of this diamond-l... | 05/06/2008 |
| 7364925 | Organic light emitting device having a protective barrier A method of forming a protective barrier in an organic light emitting device is disclosed, wherein the organic light emitting device is formed on a substrate and includes a plurality of layers of materials, the plurality of layers of materials including an organic l... | 04/29/2008 |
| 7309659 | Silicon-containing resist to pattern organic low k-dielectrics The disclosure provides methods to mitigate and/or eliminate problems associated with removal of carbon-based resists from organic low k dielectrics. The methods include forming an organic low k dielectric layer over a semiconductor substrate, forming a capping laye... | 12/18/2007 |
| 7138338 | Method and composite hard mask for forming deep trenches in a semiconductor substrate A method and structure for forming deep trenches in a semiconductor substrate is provided. The method comprises: providing a semiconductor substrate; forming a pad oxide layer on the semiconductor substrate; forming a pad nitride layer on the pad oxide layer; formin... | 11/21/2006 |
| 7138341 | Process for making a memory structure An exemplary method for making a memory structure comprises forming a first hard mask layer, forming at least one mask layer above the first hard mask layer, patterning the at least one mask layer, etching the at least one mask layer to form an opening having a firs... | 11/21/2006 |
| 6703304 | Dual damascene process using self-assembled monolayer and spacers A method of fabricating a trench on an integrated circuit having first and second insulative layers includes providing a layer of material over the insulative layers; forming a first self-assembled monolayer on the layer of material; etching the first sel... | 03/09/2004 |
| 6703690 | Apparatus for reducing isolation stress in integrated circuits Mechanical stress is diminished by forming an oxidation mask with silicon nitride having a graded silicon concentration. Grading is accomplished by changing the silicon content in the silicon nitride. The silicon nitride can be graded in a substantially l... | 03/09/2004 |
| 6696363 | Method of and apparatus for substrate pre-treatment The present invention relates generally to a method and apparatus for converting a precursor material, preferably organometallic, to a film, preferably metal-containing, that is adherent to at least a portion of a substrate. Both method and apparatus incl... | 02/24/2004 |
| 6689682 | Multilayer anti-reflective coating for semiconductor lithography A multilayer electrically conductive stack is formed in a semiconductor device prior to one step of photolithography. In this multilayer electrically conductive stack, alternate layers of the stack contain materials that differ in their refractive indices... | 02/10/2004 |
| 6682991 | Growth method of a nitride III-V compound semiconductor, manufacturing method of a semiconductor device, and semiconductor device When making a growth mask on a substrate and using the growth mask to selectively grow nitride III-V compound semiconductors on the substrate, a multi-layered film including a nitride forming at least its top surface is used as the growth mask. The growth... | 01/27/2004 |
| 6667237 | Method and apparatus for patterning fine dimensions A process of forming fine repetitive geometries using a mask having large mask dimensions. The pitch of the masking pattern on the mask is divided by the process to obtain a smaller pitch in the fine repetitive geometries. At least two working materials a... | 12/23/2003 |
| 6664173 | Hardmask gate patterning technique for all transistors using spacer gate approach for critical dimension control An electrical element may be made by providing a hardmask unit that has a double gate stack with a first gate layer, a first hardmask layer formed over the first gate layer, a second gate layer formed over the first hardmask layer, and a second hardmask l... | 12/16/2003 |
| 6664026 | Method of manufacturing high aspect ratio photolithographic features An etch barrier to be used in a photolithograph process is disclosed. A silicon rich etch barrier is deposited on a substrate using a low energy deposition technique. A diamond like carbon layer is deposited on the silicon rich etch barrier. Photoresist i... | 12/16/2003 |
| 6653735 | CVD silicon carbide layer as a BARC and hard mask for gate patterning A BARC comprising materials having a lower pinhole density than that of silicon oxynitride and materials having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of polysilicon than that of amorphous carbon is emplo... | 11/25/2003 |
| 6653058 | Methods for reducing profile variation in photoresist trimming A method of removing photoresist material from a semiconductor substrate includes providing a semiconductor substrate having a patterned photoresist mask. A layer comprised of polymer material is formed over the patterned photoresist mask. The layer compr... | 11/25/2003 |
| 6638441 | Method for pitch reduction A method for pitch reduction is disclosed. The method can form a pattern with a pitch 1/3 the original pitch formed by available photolithography technologies by only using one photo mask or one pattern transfer process, self-aligned etching back processe... | 10/28/2003 |
| 6638833 | Process for the fabrication of integrated devices with reduction of damage from plasma The process for the fabrication of an electronic device has the steps of forming a layer to be etched on top of a substrate in a wafer of semiconductor material; depositing a masking layer; and carrying out a plasma etch to define the geometry of the laye... | 10/28/2003 |
| 6638666 | Substrate for a transfer mask, transfer mask, and method of manufacturing the transfer mask A substrate for a transfer mask, which comprises a first silicon layer formed of monocrystalline silicon, a silicon oxide film formed on the first silicon layer and having a thickness ranging from 0.2 to 0.8 μm, and a second silicon layer formed on the s... | 10/28/2003 |
| 6624080 | Method of fabricating nickel etching mask There is provided a metal etching mask fabrication method. Chrome is first sputtered on a silica layer and a photoresist, which is thicker than the chrome layer, is deposited on the chrome layer. The photoresist layer is patterned, a first nickel is sputt... | 09/23/2003 |
| 6617215 | Memory wordline hard mask A manufacturing method for a MirrorBit.RTM. Flash memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric material. First and second bitlines are implanted and a wordline material is deposited. A hard mask material ... | 09/09/2003 |
| 6617085 | Wet etch reduction of gate widths A method of forming sublithography gate lengths involves the steps of patterning the layer of resist above the gate stack (including a gate layer, hardmask layer and etch-control layer) to a desired gate length and etching the etch-control layer and the h... | 09/09/2003 |
| 6610609 | Compatibilization treatment Disclosed are compositions and methods for improving compatibility of imaging layers with dielectric layers. Also disclosed are methods of reducing or eliminating poisoning of photoresists during electronic device manufacture.... | 08/26/2003 |
| 6602798 | Method and apparatus for reducing isolation stress in integrated circuits Stress resulting from silicon nitride is diminished by forming an oxidation mask with silicon nitride having a graded silicon concentration. Grading is accomplished by changing the silicon content in the silicon nitride by varying the amount of hydride, s... | 08/05/2003 |
| 6500772 | Methods and materials for depositing films on semiconductor substrates A method of depositing a film on a substrate, comprising placing the substrate in the presence of plasma energy, and contacting the substrate with a reactive gas component comprising a compound of the formula (R--NH)4-n SiXn, wherein... | 12/31/2002 |
| 6489238 | Method to reduce photoresist contamination from silicon carbide films Silicon carbide layers are often used as hardmask layers in semiconductor processing. The photoresist used to pattern the silicon carbide layers during the hardmask patterning process can become poisoned by the silicon carbide layer and remain attached to... | 12/03/2002 |
| 6414376 | Method and apparatus for reducing isolation stress in integrated circuits Stress resulting from silicon nitride is diminished by forming an oxidation mask with silicon nitride having a graded silicon concentration. Grading is accomplished by changing the silicon content in the silicon nitride by varying the amount of hydride, s... | 07/02/2002 |
| 6410421 | Semiconductor device with anti-reflective structure and methods of manufacture A semiconductor devices includes an anti-reflective structure for use in patterning metal layers in semiconductor devices. The anti-reflective structure is made, at least in part, using indium tin oxide. The anti-reflective structure is especially useful ... | 06/25/2002 |
| 6387771 | Low temperature oxidation of conductive layers for semiconductor fabrication A method for forming a valve metal oxide for semiconductor fabrication in accordance with the present invention is disclosed and claimed. The method includes the steps of providing a semiconductor wafer, depositing a valve metal on the wafer, placing the ... | 05/14/2002 |
| 6380610 | Dislocation free local oxidation of silicon with suppression of narrow space field oxide thinning effect A novel design of an oxidation mask for improved control of birds beak and more specifically for tailoring and smoothing the field oxide isolation profile in the vicinity of the birds beak. The mask design is particularly advantageous for narrow field iso... | 04/30/2002 |
| 6297114 | Semiconductor device and process and apparatus of fabricating the same A semiconductor device having a gate electrode on a Si-substrate through a gate oxide film; a first impurity diffusion region having a conductivity type reversed to a well which will form a part of source and drain regions in the two opposing sides of the... | 10/02/2001 |
| 6291352 | Method of manufacturing a semiconductor device Amorphous or polycrystalline silicon layers are sometimes used in the metallization steps of IC processes, for example as antireflex coatings or as etching stopper layers for etching back of tungsten. A problem is that such a layer cannot be provided by C... | 09/18/2001 |
| 6287975 | Method for using a hard mask for critical dimension growth containment A method for containing the critical dimension growth of the feature on a semiconductor substrate includes placing a substrate with a hard mask comprised of a reactive metal or an oxidized reactive metal in a chamber and etching the wafer. The method furt... | 09/11/2001 |
| 6245669 | High selectivity Si-rich SiON etch-stop layer The present invention provides an anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer and two compatible oxide etch processes. The Si-Rich Silicon oxynitride (SiON) etch barrier layer can be used as a hard mask in a dual damascene structu... | 06/12/2001 |
| 6239033 | Manufacturing method of semiconductor device After making a GaN FET by growing GaN semiconductor layers on the surface of a sapphire substrate, the bottom surface of the sapphire substrate is processed by lapping, using an abrasive liquid containing a diamond granular abrasive material and reducing ... | 05/29/2001 |
| 6239008 | Method of making a density multiplier for semiconductor device manufacturing A method of manufacturing a semiconductor device with increased density of structures that have at least one dimension less than that provided by the lithography system being used in the manufacturing process.... | 05/29/2001 |
| 6238999 | Isolation region forming methods In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending ther... | 05/29/2001 |
| 6207573 | Differential trench open process In accordance with the invention, a method for opening holes for semiconductor fabrication includes the steps of providing a pad stack on a substrate, forming a hard mask layer on the pad stack, the hard mask layer selectively removable relative to the pa... | 03/27/2001 |
