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| Number | Title | Issue Date |
| 7296245 | Combined e-beam and optical exposure semiconductor lithography Combined e-beam and optical exposure lithography for semiconductor fabrication is disclosed. E-beam direct writing to is employed to create critical dimension (CD) areas of a semiconductor design on a semiconductor wafer. Optical exposure lithography is employed to ... | 11/13/2007 |
| 7202095 | Method for measuring silicide proportion, method for measuring annealing temperature, method for fabricating semiconductor device and x-ray photo receiver A measurement substrate 100 in which a silicon oxide film 102, a polysilicon layer 103 and a titanium silicide layer 104 are formed over a silicon substrate 101 in this order is prepared. The measurement substrate 100 is irr... | 04/10/2007 |
| 6436810 | Bi-layer resist process for dual damascene The current invention teaches the use of e-beam patterning techniques for forming contact and via holes of diameter less than about 0.15 microns down to 0.05 microns. E-beam lithography has higher resolution (down to 30-50 nanometers) as compared to 130-1... | 08/20/2002 |
| 6319566 | Method of molecular-scale pattern imprinting at surfaces A method for mask-free molecular or atomic patterning of surfaces of reactive solids is disclosed. A molecular-scale pattern of adsorbate molecules is used in place of the conventional macroscopic "mask". Molecules adsorb at surfaces in patterns, governed... | 11/20/2001 |
| 6239008 | Method of making a density multiplier for semiconductor device manufacturing A method of manufacturing a semiconductor device with increased density of structures that have at least one dimension less than that provided by the lithography system being used in the manufacturing process.... | 05/29/2001 |
| 6156393 | Method of molecular-scale pattern imprinting at surfaces A method for mask-free molecular or atomic patterning of surfaces of reactive solids is disclosed. A molecular-scale pattern of adsorbate molecules is used in place of the conventional macroscopic "mask". Molecules adsorb at surfaces in patterns, governed... | 12/05/2000 |
| 6153499 | Method of manufacturing semiconductor device A first resist film for EB exposure, a buffer film, and a second resist film for i-line exposure are applied sequentially onto a substrate. Thereafter, the second resist film and the buffer film are subjected to patterning for forming a first opening. The... | 11/28/2000 |
| 6150070 | Method of creating optimal profile in single layer photoresist A process for forming a photoresist image on a substrate and a process for forming metal contacts on a substrate are described. The process of forming a photoresist image includes depositing a positive working photoresist composition onto a semiconductor ... | 11/21/2000 |
| 6127272 | Method of electron beam lithography on very high resistivity substrates A method of performing electron beam lithography on high resistivity substrates including forming semiconductor material on a high resistivity substrate and etching the semiconductor material to form mesas with electrically interconnecting bridges between... | 10/03/2000 |
| 5876901 | Method for fabricating semiconductor device The method for fabricating a semiconductor device according to the present includes the steps of: forming an opening in an electron beam resist layer formed on a semiconductor substrate; forming an opening in a photoresist layer formed on the electron beam ... | 03/02/1999 |
| 5837423 | Semiconductor IC device fabricating method Either a chemical amplification positive electron beam resist film or a chemical amplification negative electron beam resist film is used selectively according to an IC fabricating process when forming a minute IC pattern by using, as a mask, a resist pat... | 11/17/1998 |
| 5776820 | Method of forming a high-frequency transistor T gate electrode A method of forming a T-type gate electrode of a high-frequency transistor having excellent high-frequency power transfer characteristic with no concave portions and protrusions. A first resist pattern having a first relatively narrow opening is formed on... | 07/07/1998 |
| 5770336 | Lithography mask and fabrication method thereof A lithography mask and a method for fabricating a mask are disclosed. The method includes the steps of forming a plurality of insulating film patterns on a semiconductor substrate, forming a plurality of doped regions in the semiconductor substrate, formi... | 06/23/1998 |
| 5702620 | Ultrafine pattern forming method and ultrafine etching method using calixarene derivative as negative resist A resist film consisting of 5,11,17,23,29,35-hexachloromethyl-37, 38,39,40,41,42-hexamethoxycalix›6!arene sensitive to a high-energy beam and soluble to a solvent is formed on a substrate etchable by a dry etching, has a selective region thereof exposed ... | 12/30/1997 |
| 5693548 | Method for making T-gate of field effect transistor A method for making a T-shaped gate of a field effect transistor is disclosed. The method includes the steps of sequentially depositing first and second photoresist layers on a semiconductor substrate and performing an exposure using electron beams having... | 12/02/1997 |
| 5641715 | Semiconductor IC device fabricating method Either a chemical amplification positive electron beam resist film or a chemical amplification negative electron beam resist film is used selectively according to an IC fabricating process when forming a minute IC pattern by using, as a mask, a resist pat... | 06/24/1997 |
| 5539222 | High yield sub-micron gate FETs Yields of FETs such as HEMTs are significantly improved by establishing an elongate gate contact opening in a patterning material with the patterning material overhanging the opening along both its elongate sides and its ends. A contact metal is next evap... | 07/23/1996 |
| 5468595 | Method for three-dimensional control of solubility properties of resist layers An electron beam exposure method for controlling the solubility of resist layers used in a variety of lithography processes, to permit removal of the resist material from selected positions and depths in the resist. By controlling the energy of a uniform ... | 11/21/1995 |
| 5432119 | High yield electron-beam gate fabrication method for sub-micron gate FETS Yields of FETs such as HEMTs are significantly improved by establishing an elongate gate contact opening in a patterning material with the patterning material over-hanging the opening along both its elongate sides and its ends. A contact metal is next eva... | 07/11/1995 |
| 5350485 | High-resolution lithography and semiconductor device manufacturing method A lithographic method for forming a mask pattern is useful for etching wiring or insulator layers on a substrate. A catalyst generation layer and a latent image formation layer are formed on the target layer prior to application of actinic radiation to ac... | 09/27/1994 |
| 5166888 | Fabrication of particle beam masks A method for automatically splitting a layout of a hole pattern into two complementary arrangements for x-ray, electron beam, ion beams, i.e., particle beam masks. The method determines all inside and outside corners of said pattern and determining a stab... | 11/24/1992 |
| 5102688 | Fine pattern forming process A positive type fine resist pattern can be formed at a high sensitivity at a high precision by using, as a resist film for a di-layer resist, a mixture or alternating copolymer of a silicon-containing resin and a polysulfone.... | 04/07/1992 |
| 5091047 | Plasma etching using a bilayer mask A bilayer mask is utilized for etching a primary layer, which may be either an aluminum metallization layer or a dielectric layer. The bilayer mask includes both a thin resist layer and a metal imaging layer. The thin resist layer provides for high resolu... | 02/25/1992 |
| 5045150 | Plasma etching using a bilayer mask A bilayer mask is utilized for etching a primary layer, which may be either an aluminum metallization layer or a dielectric layer. The bilayer mask includes both a thin resist layer and a metal imaging layer. The thin resist layer provides for high resolu... | 09/03/1991 |
| 4810617 | Treatment of planarizing layer in multilayer electron beam resist An improved electron beam resist structure comprises an organic planarizing layer which has been treated with an ion beam for a time sufficient to render it conductive and an electron beam resist layer thereover. The electron beam resist layer is preferab... | 03/07/1989 |
| 4748132 | Micro fabrication process for semiconductor structure using coherent electron beams As a process for fabricating uniform patterns fine enough to produce a quantum size effect, the use of electron halography is proposed. Disclosed examples employing a process are methods of manufacturing a semiconductors laser whose threshold current is a... | 05/31/1988 |
| 4702993 | Treatment of planarizing layer in multilayer electron beam resist An improved electron beam resist structure comprises an organic planarizing layer which has been treated with an ion beam for a time sufficient to render it conductive and an electron beam resist layer thereover. The electron beam resist layer is preferab... | 10/27/1987 |
| 4642672 | Semiconductor device having registration mark for electron beam exposure This invention relates to a structure of a registration mark for electron beam exposure technique. The mark comprises a lower metal film formed on a semiconductor substrate such as GaAs substrate having high electrical resistivity, and a upper metal film ... | 02/10/1987 |
| 4603473 | Method of fabricating integrated semiconductor circuit A method of fabricating an integrated semiconductor circuit device having a plurality of layers of circuit patterns, comprising forming the circuit pattern of at least one of the above mentioned layers by a direct exposure method using an electron beam, a... | 08/05/1986 |
| 4595649 | Glassy TiO2 polymer films as electron beam charge dissipation layers The use of TiO2 spin-on glass films for reduction of electrostatic charging of a semiconductor substrate upon electron beam exposure is described. Specifically, the disclosure relates to electron beam lithographic processing during semiconducto... | 06/17/1986 |
| 4578343 | Method for producing field effect type semiconductor device A method for producing a field effect type semiconductor device includes the steps of forming a semiconductor active layer on a substrate, forming a resist layer on the semiconductor active layer, exposing a first portion of the resist layer in accordance... | 03/25/1986 |
| 4557995 | Method of making submicron circuit structures Double sided lithography is disclosed for fabricating ultra-small multilayer microcircuit structures without need for any intermediate realignment and without need for any intermediate layer deposition involving re-establishment of surface planarity. Micr... | 12/10/1985 |
| 4489241 | Exposure method with electron beam exposure apparatus An exposure method with an electron beam exposure apparatus in which an electron beam is emitted onto a substrate such as a silicon wafer on which an electron-beam sensitive resist is coated, thereby directly forming or writing patterns. A substrate havin... | 12/18/1984 |
| 4487795 | Method of forming patterned conductor lines A conductor pattern consisting of conductor lines is formed in an electronic device by an electron-beam lithography process using a positive resist. After the formation of a positive resist layer on a conductive layer, a linear pattern of latent images is... | 12/11/1984 |
| 4458129 | Discharge device and method for use in processing semiconductor devices An electrical discharge is applied to a wafer mounted in a wafer holder. The wafer includes at least one conducting region covered by an insulating layer. The discharge causes a conductive channel from the conductive region through the insulating layer. T... | 07/03/1984 |
| 4451738 | Microcircuit fabrication The fabrication of a microcircuit by beam lithography requires an economic distribution of processing time between the high resolution portions of the exposure pattern and areas of much lower resolution. At least one ion beam provides the high resolution ... | 05/29/1984 |
| 4394182 | Microelectronic shadow masking process for reducing punchthrough A process for forming a doped region in a substrate which is in alignment with a circuit member by forming a masking member on a layer, the masking member defining the outline on the circuit member; and etching the layer employing the masking member as a ... | 07/19/1983 |
| 4350866 | Discharge device and method for use in processing semiconductor devices An electrical discharge is applied to a wafer mounted in a wafer holder. The wafer includes at least one conducting region covered by an insulating layer. The discharge causes a conductive channel from the conductive region through the insulating layer. T... | 09/21/1982 |
| 4348804 | Method of fabricating an integrated circuit device utilizing electron beam irradiation and selective oxidation Dielectric isolation through electron beam irradiation is applied to a method of fabricating a semiconductor device. Upon forming an insulated gate field effect semiconductor device (FET) in a semiconductor layer on an insulation substrate, the insulated ... | 09/14/1982 |
| 4323638 | Reducing charging effects in charged-particle-beam lithography In a charged-particle-beam lithographic system, charge accumulation on the workpiece during alignment or writing can cause significant pattern placement errors. A film (16) formed directly under the resist layer (56) to be patterned is utilized as a charg... | 04/06/1982 |
