"Flight by machines heavier than air is unpractical and insignificant, if not utterly impossible."
Simon Newcomb, astronomer ; Said in 1902, less than two years before the first flight at Kitty Hawk
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| Number | Title | Issue Date |
| 7442640 | Semiconductor device manufacturing methods Methods of manufacturing a semiconductor device including a high-voltage device region and a low-voltage device region are provided. An illustrated method includes forming, on a substrate, a gate pattern for a high-voltage device and a low-voltage device; implanting... | 10/28/2008 |
| 7435674 | Dielectric interconnect structures and methods for forming the same Dielectric interconnect structures and methods for forming the same are provided. Specifically, the present invention provides a dielectric interconnect structure having a noble metal layer (e.g., Ru, Ir, Rh, Pt, RuTa, and alloys of Ru, Ir, Rh, Pt, and RuTa) that is... | 10/14/2008 |
| 7432208 | Method of manufacturing suspension structure A method of manufacturing a suspension structure including providing a substrate, forming a first photoresist pattern on the substrate, heating the first photoresist pattern to harden it as a sacrificial layer, forming a second photoresist pattern on the substrate a... | 10/07/2008 |
| 7397107 | Ferromagnetic capacitor An integrated circuit capacitor having a bottom plate 50a, a dielectric layer 250′, and a ferromagnetic top plate 20a. ... | 07/08/2008 |
| 7391086 | Conductive contacts and methods for fabricating conductive contacts for elctrochemical planarization of a work piece Conductive contacts and methods for fabricating conductive contacts for electrochemical mechanical planarization are provided. A conductive contact in accordance with an exemplary embodiment of the invention includes, but is not limited to, a first conductive surfac... | 06/24/2008 |
| 7387956 | Refractory metal-based electrodes for work function setting in semiconductor devices The present invention provides, in one embodiment, a gate structure (100). The gate structure comprises a gate dielectric (105) and a gate (110). The gate dielectric includes a refractory metal and is located over a semiconductor substrate (1... | 06/17/2008 |
| 7374964 | Atomic layer deposition of CeO/AlOfilms as gate dielectrics The use of atomic layer deposition (ALD) to form a nanolaminate layered dielectric layer of cerium oxide and aluminum oxide acting as a single dielectric layer with a ratio of approximately two to one between the cerium oxide and the aluminum oxide, and a method of ... | 05/20/2008 |
| 7372090 | Magnetic random access memory device and method of forming the same Example embodiments of the present invention disclose a semiconductor memory device and a method of forming a memory device. A semiconductor memory device may include a digit line disposed on a substrate, an intermediate insulating layer covering the digit line, a m... | 05/13/2008 |
| 7368796 | Metal gate engineering for surface P-channel devices A semiconductor device, such as a CMOS device, having gates with a high work function in PMOS regions and low work functions in NMOS regions and a method of producing the same. Using nitrogen implantation or plasma annealing, a low work function W (or CoSix | 05/06/2008 |
| 7363971 | Method and apparatus for maintaining a multi-chip module at a temperature above downhole temperature Methods and systems for operating integrated circuits at temperatures higher than expected ambient temperatures. The heating may be of entire circuit boards, portions of the circuit boards (such as the components within a multiple-chip module) and/or single devices.... | 04/29/2008 |
| 7341908 | Semiconductor device and method of manufacturing the same Provided are a semiconductor device including a reliable interconnect and a method of manufacturing the same. The semiconductor device includes a substrate, an inter-metal dielectric (IMD) pattern having an opening, an amorphous metallic nitride layer formed on the ... | 03/11/2008 |
| 7335595 | Silicide formation using a low temperature anneal process A silicide 160 is formed in exposed silicon on a semiconductor wafer 10 by a method that includes forming a thin interface layer 140 over the semiconductor wafer 10 and performing a first low temperature anneal to create the silicide 1... | 02/26/2008 |
| 7332442 | Systems and methods for forming metal oxide layers A method of forming (and apparatus for forming) a metal oxide layer, preferably a dielectric layer, on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process and ozone with one or more metal organo-amine precursor... | 02/19/2008 |
| 7326648 | Semiconductor device and fabrication process of forming silicide layer on a polysilicon pattern by reducing thickness of metal layer before forming silicide layer on the polysilicon pattern A semiconductor device includes a substrate having first and second device regions separated from each other by a device isolation region, a first field effect transistor having a first polysilicon gate electrode and formed in the first device region, a second field... | 02/05/2008 |
| 7321154 | Refractory metal-based electrodes for work function setting in semiconductor devices The present invention provides, in one embodiment, a gate structure (100). The gate structure comprises a gate dielectric (105) and a gate (110). The gate dielectric includes a refractory metal and is located over a semiconductor substrate (1... | 01/22/2008 |
| 7314829 | Method and apparatus for polysilicon resistor formation Some embodiments of the present invention include implanting and annealing polysilicon lines to form a silicide blocking layer that may inhibit silicide formation. The silicide blocking layer may facilitate fabrication of polysilicon resistors. ... | 01/01/2008 |
| 7312151 | System for ultraviolet atmospheric seed layer remediation The present invention provides a system for removing organic contaminants (216) from a copper seed layer that has been deposited on a semiconductor substrate (206). The present invention provides a housing (204) to enclose the semiconductor subs... | 12/25/2007 |
| 7300870 | Systems and methods of forming refractory metal nitride layers using organic amines A method of forming (and apparatus for forming) refractory metal nitride layers (including silicon nitride layers), such as a tantalum nitride barrier layer, on a substrate by using an atomic layer deposition process (a vapor deposition process that includes a plura... | 11/27/2007 |
| 7276444 | Method for processing interior of vapor phase deposition apparatus, method for depositing thin film and method for manufacturing semiconductor device A method for depositing a metal compound film on the wafer by using a vapor phase deposition apparatus 100, including: forming a thin film on the wafer in an interior of the vapor phase deposition apparatus 100 by introducing a source gas for the metal... | 10/02/2007 |
| 7276796 | Formation of oxidation-resistant seed layer for interconnect applications An interconnect structure of the single or dual damascene type and a method of forming the same, which substantially reduces the surface oxidation problem of plating a conductive material onto a noble metal seed layer are provided. In accordance with the present inv... | 10/02/2007 |
| 7268077 | Carbon nanotube reinforced metallic layer A method and apparatus including an interconnect structure having a surface, a plurality of nanotubes disposed adjacent to the surface, and a metallic layer disposed adjacent to the surface and substantially including the nanotubes. An assembly may include a first e... | 09/11/2007 |
| 7262504 | Multiple stage electroless deposition of a metal layer A multiple stage method of electrolessly depositing a metal layer is presented. This method may have the two main stages of first forming a thin metal layer on a metal surface using an electroless plating solution containing activating agents that are highly reactiv... | 08/28/2007 |
| 7259057 | Method for forming capacitor of semiconductor device Disclosed is a method for forming a capacitor of a semiconductor device capable of improving the film quality of a dielectric film. The method includes the steps of providing a semiconductor substrate having a storage node contact; forming a metal storage electrode ... | 08/21/2007 |
| 7250379 | Method of forming metal oxide using an atomic layer deposition process In a method of forming a metal oxide, an organic metal compound represented by the following chemical formula is introduced into a chamber to chemisorb the organic metal compound onto a substrate, M[L1]x[L2]y where M represents a metal, L1 and L2... | 07/31/2007 |
| 7241632 | MTJ read head with sidewall spacers Following CMP, a magnetic tunnel junction stack may protrude through the oxide that surrounds it, making it susceptible to possible shorting to its sidewalls. The present invention overcomes this problem by depositing silicon nitride spacers on these sidewalls prior... | 07/10/2007 |
| 7229920 | Method of fabricating metal silicide layer A method of fabricating a metal silicide layer over a substrate is provided. First, a hard mask layer is formed over a gate formed on a substrate and a portion of the substrate is exposed. Thereafter, a first metal silicide layer, which is a cobalt silicide or a tit... | 06/12/2007 |
| 7217981 | Tunable temperature coefficient of resistance resistors and method of fabricating same Tunable TCR resistors incorporated into integrated circuits and a method fabricating the tunable TCR resistors. The tunable TCR resistors including two or more resistors of two or more different materials having opposite polarity and different magnitude TCRs, the sa... | 05/15/2007 |
| 7214988 | Metal oxide semiconductor transistor A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a ... | 05/08/2007 |
| 7215006 | Plating seed layer including an oxygen/nitrogen transition region for barrier enhancement An interconnect structure which includes a plating seed layer that has enhanced conductive material, preferably, Cu, diffusion properties is provided that eliminates the need for utilizing separate diffusion and seed layers. Specifically, the present invention provi... | 05/08/2007 |
| 7166518 | System and method for providing a self heating adjustable TiSiresistor A system and method is disclosed for providing a self heating adjustable titanium disilicon (TiSi2) resistor. A triangularly shaped layer of polysilicon is placed a layer of insulation material. A layer of titanium is applied over the polysilicon and heat... | 01/23/2007 |
| 7160754 | P-type OFET with fluorinated channels The present invention provides an organic field-effect transistor (OFET) and a method of fabricating the OFET. The OFET, configured to function as a p-type semiconductor, includes a substrate having a top surface and a semiconductor layer located over the top surfac... | 01/09/2007 |
| 7148118 | Methods of forming metal nitride, and methods of forming capacitor constructions The invention encompasses methods of forming metal nitride proximate dielectric materials. The metal nitride comprises two portions, with one of the portions being nearer the dielectric material than the other. The portion of the metal nitride nearest the dielectric... | 12/12/2006 |
| 7098516 | Refractory metal-based electrodes for work function setting in semiconductor devices The present invention provides, in one embodiment, a gate structure (100). The gate structure comprises a gate dielectric (105) and a gate (110). The gate dielectric includes a refractory metal and is located over a semiconductor substrate (1... | 08/29/2006 |
| 7074683 | Semiconductor devices and methods of fabricating the same A semiconductor device comprises a device isolation layer disposed in a portion of a substrate of first conductivity type. An outline of the device isolation layer defines an active region of the substrate. An impurity diffused region of second conductivity type may... | 07/11/2006 |
| 7067439 | ALD metal oxide deposition process using direct oxidation Methods of forming metal compounds such as metal oxides or metal nitrides by sequentially introducing and then reacting metal organic compounds with ozone or with oxygen radicals or nitrogen radicals formed in a remote plasma chamber. The metal compounds have surpri... | 06/27/2006 |
| 6993828 | Method for manufacturing metal thin film resistor A metal resistor and a method for manufacturing the resistor are provided. A first insulation film is formed on a substrate, a photosensitive film is applied on the insulation film, and an insulation film pattern is formed by patterning the insulation film. After a ... | 02/07/2006 |
| 6703666 | Thin film resistor device and a method of manufacture therefor The present invention provides a thin film resistor and method of manufacture therefor. The thin film resistor comprises a resistive layer located on a first dielectric layer, first and second contact pads located on the resistive layer, and a second diel... | 03/09/2004 |
| 6696733 | Semiconductor devices including electrode structure A semiconductor device in certain embodiments includes an insulating layer provided above the upper surface of a semiconductor substrate, and a capacitive element section and a resistance element section formed above the insulating layer. In the capacitiv... | 02/24/2004 |
| 6667537 | Semiconductor devices including resistance elements and fuse elements A semiconductor device may have an insulating layer comprising a silicon oxide film or the like formed so as to cover an entire upper surface of a semiconductor substrate. A resistance element comprising MoSix is formed on the insulating layer.... | 12/23/2003 |
| 6664166 | Control of nichorme resistor temperature coefficient using RF plasma sputter etch A method for processing a partially fabricated semiconductor wafer having a layer of nichrome resistor material patterned to form a plurality of nichrome resistors on a surface of the wafer includes performing a wet pre-metallization cleaning step on the ... | 12/16/2003 |