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| Number | Title | Issue Date |
| 7030464 | Semiconductor device and method of manufacturing the same A technology of restraining junction leakage in a semiconductor device is to be provided. There is provided a semiconductor device provided with a semiconductor substrate, a gate electrode 9 formed on the semiconductor substrate, and a source/drain region for... | 04/18/2006 |
| 7002210 | Semiconductor device including a high-breakdown voltage MOS transistor On a semiconductor substrate, a well is formed. In the well, one MOS transistor including a gate electrode, a source region, a source field limiting layer and a source/drain region, and another MOS transistor including a gate electrode, a drain electrode, a drain fi... | 02/21/2006 |
| 7002218 | Low capacitance ESD-protection structure under a bond pad An ESD-protection structure is located substantially under an integrated circuit bond pad. This ESD-protection structure is formed as a low capacitance structure by inserting a forward diode between the bond pad and the ESD clamp circuit. Placing the ESD-protection ... | 02/21/2006 |
| 6597038 | MOS transistor with double drain structure for suppressing short channel effect The present invention discloses a semiconductor device, and a method of fabricating the same, where the semiconductor device has a gate electrode, a source-drain diffused layer of a first conductivity type, and a sidewall insulating film formed on the sid... | 07/22/2003 |
| 6593638 | Lightly donor doped electrodes for high-dielectric-constant materials A preferred embodiment of this invention comprises a conductive lightly donor doped perovskite layer (e.g. lightly La doped BST 34), and a high-dielectric-constant material layer (e.g. undoped BST 36) overlaying the conductive lightly donor doped perovski... | 07/15/2003 |
| 6479356 | Method of manufacturing a semiconductive device with an enhanced junction breakdown strength A gate insulating film and gate electrodes are formed on a substrate containing N-type impurities such as P or As. Under the gate insulating film is a gate region on both sides of which are a first and a second source drain region. The gate region is furn... | 11/12/2002 |
| 6459140 | Indium-enhanced bipolar transistor A method to improve the characteristics of bipolar silicon high-frequency transistor by adding indium into the base of the transistor is described. Instead of replacing boron in the base with indium to improve the beta-Early voltage product, at the price ... | 10/01/2002 |
| 6400002 | Methods of forming field effect transistors and related field effect transistor constructions Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate ... | 06/04/2002 |
| 6081007 | Semiconductor device comprising MIS transistor with high concentration channel injection region A gate insulating film and gate electrodes are formed on a substrate containing N-type impurities such as P or As. Under the gate insulating film is a gate region on both sides of which are a first and a second source drain region. The gate region is furn... | 06/27/2000 |
| 5969398 | Method for producing a semiconductor device and a semiconductor device A method for producing a semiconductor device which comprises a step for forming a gate electrode on a main surface of a semiconductor substrate via a gate oxide film, and a step for directing plasma ions with a gas mixture comprising a first gas containi... | 10/19/1999 |
| 5956593 | Semiconductor device comprising an MOS capacitance An improved semiconductor device including an MOS capacitance is provided, having enhanced MOS capacitance accuracy. A well of a first conductivity type is formed at the main surface of a semiconductor substrate. The above-described well is removed immedi... | 09/21/1999 |
| 5952693 | CMOS semiconductor device comprising graded junctions with reduced junction capacitance A CMOS semiconductor device is formed having an N-channel transistor comprising a graded junction with reduced junction capacitance. The graded junction is achieved by forming a second sidewall spacer on the gate electrode, after source/drain implantation... | 09/14/1999 |
| 5719424 | Graded LDD implant process for sub-half-micron MOS devices A process for grading the junctions of a lightly doped drain (LDD) N-channel MOSFET by performing a low dosage phosphorous implant after low and high dosage arsenic implants have been performed during the creation of the N-LDD regions and N+ source and dr... | 02/17/1998 |
| 5408125 | Semiconductor process for manufacturing semiconductor device with increased operating voltages A method of manufacturing semiconductor devices with increased operating voltages is described. A dopant of a second conductivity type is implanted into a region of a first epitaxial layer of the first conductivity type to form a buried layer. A substanti... | 04/18/1995 |
| 5391909 | Detection of electron-beam scanning of a substrate The scanning of an operating integrated circuit (IC) substrate by an electron (e)-beam is detected by providing conductive plates in the substrate, and triggering a charge-sensitive mechanism such as a field effect transistor (FET) when an e-beam has scan... | 02/21/1995 |
| 5389809 | Silicided MOS transistor A process for forming N-channel MOS sources and drains, by implanting both phosphorus and arsenic. The high diffusivity of phosphorus causes it to diffuse in advance of the bulk of the arsenic, so that, after annealing, the source/drain regions have grade... | 02/14/1995 |
| 5150177 | Schottky diode structure with localized diode well An improved Schottky diode structure (4) is formed by retrograde diffusing an N+ concentration of relatively fast diffusing atoms, preferably Phosphorus atoms, to form a localized diode NWell (6) as the diode substrate for the diode. A buried d... | 09/22/1992 |
| 5021851 | NMOS source/drain doping with both P and As A process for forming N-channel MOS sources and drains, by implanting both phosphorus and arsenic. The high diffusivity of phosphorus causes it to diffuse in advance of the bulk of the arsenic, so that, after annealing, the source/drain regions have grade... | 06/04/1991 |
| 4967089 | Pulsed optical source A compact pulsed optical source of near to ultraviolet wavelength energy adapted to be connected to an external power source. The optical source includes a device for emitting photons, apparatus for transforming photons into photoelectrons, apparatus for ... | 10/30/1990 |
| 4851360 | NMOS source/drain doping with both P and As A process for forming N-channel MOS sources and drains, by implanting both phosphorus and arsenic. The high diffusivity of phosphorus causes it to diffuse in advance of the bulk of the arsenic, so that, after annealling, the source/drain regions have grad... | 07/25/1989 |
| 4658277 | Two level charge imaging matrix design with stepped insulator The disclosure relates to a charge imaging matrix wherein the floating gate level closest to the substrate is used as a storage gate and the second floating gate level is used as both a field plate and a transfer gate due to the formation of a step in the... | 04/14/1987 |
| 4566175 | Method of making insulated gate field effect transistor with a lightly doped drain using oxide sidewall spacer and double implantations A transistor for VLSI devices employs a phosphorus implant and lateral diffusion performed after the sidewall oxide etch to thereby reduce the impurity concentration and provide a graded junction for the reach-through implanted region between heavily-dope... | 01/28/1986 |
| 4532537 | Photodetector with enhanced light absorption A photodetector including a light transmissive electrically conducting layer having a textured surface with a semiconductor body thereon. This layer traps incident light thereby enhancing the absorption of light by the semiconductor body. A photodetector ... | 07/30/1985 |
| 4329702 | Low cost reduced blooming device and method for making the same An image sensing device includes a wafer having a first input sensing surface region and a second charge storage surface region. A recombination layer extends along the first surface and is spaced therefrom. The method for forming the recombination layer ... | 05/11/1982 |
| 4128897 | Archival memory media and method for information recording thereon Binary information is stored in a semiconductor archival memory medium by formation of a region of an alloy, of the semiconductor material and a non-doping material, at each of a plurality of potential memory sites at which a first binary value of informa... | 12/05/1978 |
| 4081794 | Alloy junction archival memory plane and methods for writing data thereon A memory plane for an archival, non-volatile mass storage memory has a planar semiconductor diode with each of a plurality of small P-N junction diodes alloyed into the surface of its fabricated layer responsive to a selectively-actuated scanned energy be... | 03/28/1978 |
| 4021375 | Method of fabricating polycrystalline selenium imaging devices A photoconductive target for a vidicon-type camera tube, which includes a layer of polycrystalline selenium, is exposed to a diffusion cycle wherein the temperature is gradually increased from an initial baking temperature of about 50° C. to a final baki... | 05/03/1977 |
| 4021844 | Photosensitive diode array storage target A storage target comprising a photosensitive diode array which can be used to convert an optical image into an electronic image where the photo diodes are constituted by "hyper abrupt" junctions having a junction capacitance of wide dynamic range when rev... | 05/03/1977 |
| 4010487 | Semiconductor arrangement A semiconductor arrangement comprises a region of a second type of conductivity formed in a semiconductor body of a first type of conductivity from one surface thereof, an insulating layer on this surface defining an opening above the said region and a re... | 03/01/1977 |
| 3988758 | Semiconductor camera-tube target A vidicon tube target includes a three-ply semi-insulating layer structure which comprises a bottom layer of CeO2, an intermediate layer of CePbO2.sub.+x (0 | 10/26/1976 |
| 3985918 | Method for manufacturing a target for an image pickup tube A target for an image pickup tube having high sensitivity, low dark current and low amount of lag-image is manufactured by forming a hetero-junction by the evaporation process. A first layer of ZnSx Se1.sub.-x or Znu Cd | 10/12/1976 |
| 3983574 | Semiconductor devices having surface state control A semiconductor structure having a surface insulating layer formed as a grid with charges implanted in the insulating material to prevent inversion and, hence, channeling between adjacent semiconductor regions, preferably for use in a non-blooming vidicon... | 09/28/1976 |
| 3973270 | Charge storage target and method of manufacture A charge storage device of the type in which a target electrode provides a plurality of spatially distributed charge storage sites formed on an output side of a semiconductor wafer with means associated with the storage sites for sensing and converting th... | 08/03/1976 |
| 3969750 | Diffused junction capacitor and process for producing the same A diffused junction capacitor having two P+ N+ junctions, one in the semiconductor substrate and one in an epitaxial layer thereon and exhibiting high capacitance per unit area. A method for forming such a capacitor makes use of the fact ... | 07/13/1976 |
| 3966512 | Method of manufacturing targets of pickup tubes In a method of manufacturing the target of a pickup tube of the class wherein an N-type light transmitting conductive film is formed on a substrate, an N-type photoconductive film consisting of a group II-VI compound is formed on the N-type light transmit... | 06/29/1976 |
| 3956025 | Semiconductor devices having surface state control and method of manufacture A semiconductor structure having a surface insulating layer formed as a grid with charges implanted in the insulating material to prevent inversion and, hence, channeling between adjacent semiconductor regions, preferably for use in nonblooming vidicon. T... | 05/11/1976 |
