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Scientific American ; Jan. 2 edition, 1909
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| Number | Title | Issue Date |
| 7375376 | Semiconductor display device and method of manufacturing the same A semiconductor display device with an interlayer insulating film in which surface levelness is ensured with a limited film formation time, heat treatment for removing moisture does not take long, and moisture in the interlayer insulating film is prevented from esca... | 05/20/2008 |
| 7288806 | DRAM arrays The invention includes memory arrays, and methods which can be utilized for forming memory arrays. A patterned etch stop can be used during memory array fabrication, with the etch stop covering storage node contact locations while leaving openings to bitline contact... | 10/30/2007 |
| 7247902 | Semiconductor device and method of manufacturing the same A semiconductor device comprises a first metal layer, which comprises a buried metal layer connected to a diffusion layer within a substrate or to a lower-layer wiring. A first metal wiring layer, a second metal layer having a buried metal layer, and a second metal ... | 07/24/2007 |
| 7230300 | Semiconductor device with peripheral trench Conventional power MOSFETs enables prevention of an inversion in a surrounding region surrounding the outer periphery of an element region by a wide annular layer and a wide sealed metal. Since, resultantly, the area of the surrounding region is large, increase in t... | 06/12/2007 |
| 7211840 | Transistor A transistor and a semiconductor integrated circuit with a reduced layout area. Area reduction of a transistor is realized by arranging contacts at higher density. Specifically, in a transistor including a pair of impurity regions and a gate electrode 604 san... | 05/01/2007 |
| 7211867 | Thin film memory, array, and operation method and manufacture method therefor A memory cell which is formed on a fully depleted SOI or other semiconductor thin film and which operates at low voltage without needing a conventional large capacitor is provided as well as a memory cell array. The semiconductor thin film is sandwiched between firs... | 05/01/2007 |
| 7189586 | Test key for monitoring gate conductor to deep trench misalignment A test key for monitoring GC-DT misalignment is provided. Deep trench capacitors are embedded in an interlacing matrix manner. GC lines are defined on a substrate and passing over the deep trench capacitors. A first bit line contact pattern surrounded by first assis... | 03/13/2007 |
| 7135731 | Vertical DRAM and fabrication method thereof A vertical DRAM and fabrication method thereof. The vertical DRAM has a plurality of memory cells on a substrate, and each of the memory cells has a trench capacitor, a vertical transistor, and a source-isolation oxide layer in a deep trench. The main advantage of t... | 11/14/2006 |
| 7126154 | Test structure for a single-sided buried strap DRAM memory cell array A test structure for determining the electrical properties of a memory cell in a matrix-like cell array constructed on the basis of the single-sided buried strap concept has a connection between internal electrodes in the storage capacitors in two adjacent memory ce... | 10/24/2006 |
| 7034408 | Memory device and method of manufacturing a memory device A memory device includes a DRAM memory cell array, which is implemented as a 6 F×F array, and peripheral circuitry. The word lines of the memory cell array are implemented as buried word lines, and, in addition, the bit lines including the bit line contacts are mad... | 04/25/2006 |
| 6974987 | Semiconductor device A memory cell transistor and a trench capacitor are provided in a memory region, and both transistors of CMOS are provided in a logic circuit region. There are provided a bit line contact 31 and a bit line 32 extending on an inter-level dielectric 3... | 12/13/2005 |
| 6974990 | Selective polysilicon stud growth A memory cell includes either a bit line contact feature or a word line space feature that are each characterized by a contact hole bounded by insulating side walls. The contact hole is filled with a conductively doped polysilicon plug defining an upper plug surface... | 12/13/2005 |
| 6967348 | Signal sharing circuit with microelectric die isolation features A signal sharing circuit includes a first pad adapted to receive a signal and a first sharing device associated with a first microelectronic die. The first sharing device is adapted to selectively share the signal with at least a second microelectronic die on one si... | 11/22/2005 |
| 6947324 | Logic process DRAM A semiconductor integrated circuit device including a dynamic random access memory (DRAM) unit having improved signal-to-noise ratio, reduced bit line capacitance, and reduced area is provided. The DRAM unit includes a plurality of bit line pairs, each bit line pair... | 09/20/2005 |
| 6936881 | Capacitor that includes high permittivity capacitor dielectric A decoupling capacitor is formed on a semiconductor substrate that includes a silicon surface layer. A substantially flat bottom electrode is formed in a portion of the semiconductor surface layer. A capacitor dielectric overlies the bottom electrode. The capacitor ... | 08/30/2005 |
| 6930324 | Device architecture and process for improved vertical memory arrays An array process diagnosis test structure for an integrated circuit including a transistor array composed of vertical FET memory cell access transistors, which are formed into the depth of a substrate in the form of active webs which run parallel in the lateral dire... | 08/16/2005 |
| 6906371 | Wordline gate contact for an MBIT transistor array layout A DRAM memory unit contains a memory bit (mbit) transistor and a capacitive region for storing charge. The memory is configured to store data as a charge stored by the capacitive region. Each memory unit is accessed by an associated wordline and the data stored by t... | 06/14/2005 |
| 6897481 | Semiconductor devices and manufacturing methods thereof Embodiments include semiconductor devices and methods of manufacture, one of which includes a capacitor unit formed on a silicon substrate. The capacitor unit is divided into a plurality of capacitor subunits which are partitioned from each other by a separating ins... | 05/24/2005 |
| 6890841 | Methods of forming integrated circuit memory devices that include a plurality of landing pad holes that are arranged in a staggered pattern and integrated circuit memory devices formed thereby An integrated circuit memory device is formed by forming an interlevel insulating layer on a substrate. A plurality of storage node contact holes are formed in the interlayer insulating layer and are arranged in a pattern. A plurality of contact plugs are formed in ... | 05/10/2005 |
| 6876014 | Interconnection structure of a semiconductor device Concave portions and convex portions are formed on an insulating layer. First bit lines are arranged on the convex portions. A width of the first bit lines is set to L, and a space between the first bit lines is set to L+2S. Each of the first bit lines is electrical... | 04/05/2005 |
| 6872627 | Selective formation of metal gate for dual gate oxide application A new processing sequence is provided for the creation of a metal gate electrode. At least two polysilicon gate electrodes are provided over the surface of a substrate, these polysilicon gate electrodes having a relatively thick layer of gate dielectric making these... | 03/29/2005 |
| 6861691 | Selective polysilicon stud growth A memory cell includes a bit line contact feature that is characterized by a contact hole bounded by insulating side walls including first and second pairs of opposing insulating side walls. The first pair of opposing insulating side walls comprises respective layer... | 03/01/2005 |
| 6858497 | Non-volatile semiconductor memory device and a method of producing the same The present invention prevents production of residue which causes short-circuit between word lines. A memory cell comprises a channel formation region CH, charge storage films CSF each comprised of a plurality of stacked dielectric films, two storages comprised of r... | 02/22/2005 |
| 6853052 | Semiconductor device having a buffer layer against stress A semiconductor device and a method for preparing the same that can solve crack of a semiconductor film, capacitance electrodes and the like due to stress when forming a source electrode and a drain electrode in a semiconductor device having a thin film transistor a... | 02/08/2005 |
| 6849889 | Semiconductor device having storage node contact plug of DRAM (dynamic random access memory) A method for forming a storage node contact plug of a dynamic random access memory includes forming insulating layers on an overall surface of a semiconductor substrate having a plurality of buried contact plugs, etching the insulating layers down to a top surface o... | 02/01/2005 |
| 6849893 | Semiconductor circuit structure and method for fabricating the semiconductor circuit structure A circuit structure has at least two etching trenches disposed at sidewalls of a silicon block left behind during the etching of the structure. The etching trenches are disposed at angles with respect to one another that are prescribed by the form of the silicon blo... | 02/01/2005 |
| 6803669 | Integrated circuits having self-aligned metal contact structures A microelectronic contact structure, e.g., a contact structure for a capacitor electrode of a DRAM, comprises a first dielectric layer on a substrate, a conductive region disposed on a first dielectric layer, a second dielectric layer on the first dielectric layer a... | 10/12/2004 |
| 6794705 | Multi-layer Pt electrode for DRAM and FRAM with high K dielectric materials A multi-layer electrode (246) and method of fabrication thereof in which a conductive region (244) is separated from a barrier layer (222) by a first conductive liner (240) and a second conductive liner (242). First conductive laye... | 09/21/2004 |
| 6791135 | Semiconductor device with improved capacitive element and method of forming the same A semiconductor device includes: a digital circuit including a first capacitive element of metal-insulator-metal structure, and an analogue circuit including a second capacitive element of metal-insulator-metal structure. Bottom electrodes, capacitive insulation lay... | 09/14/2004 |
| 6784474 | Semiconductor memory device and method for fabricating the same A memory cell in a DRAM, which is a semiconductor memory device, is provided with a bit line 21a connected to a bit line plug 20b and a local interconnect 21b, over a first interlevel insulating film 18. A conductor s... | 08/31/2004 |
| 6747305 | Memory address decode array with vertical transistors A decoder for a memory device is provided. The decoder array includes a number of address lines and a number of output lines. The address lines and the output lines form an array. A number of vertical transistors are selectively disposed at intersections of output l... | 06/08/2004 |
| 6744089 | Self-aligned lateral-transistor DRAM cell structure A self-aligned lateral-transistor DRAM cell structure is disclosed by the present invention, in which a trench structure comprises a trench region and a trench-isolation region being formed in a side portion of the trench region and a self-aligned lateral-transistor... | 06/01/2004 |
| 6740918 | Semiconductor memory device The invention provides a semiconductor memory device having a trench part serving as an isolation area formed on semiconductor substrate, control gate used for controlling write-operation and read-operation formed orthogonally to the trench part, a source line of a ... | 05/25/2004 |
| 6707092 | Semiconductor memory having longitudinal cell structure In a semiconductor memory including a dynamic random access memory, a memory cell of the dynamic random access memory includes: a semiconductor pillar (a silicon pillar); a capacitor in which one side of the silicon pillar is used as a charge accumulation electrode;... | 03/16/2004 |
| 6707088 | Method of forming integrated circuitry, method of forming a capacitor, method of forming DRAM integrated circuitry and DRAM integrated category In one implementation, integrated circuitry includes a first capacitor electrode layer received over a substrate. A capacitor dielectric layer is received over the first capacitor electrode layer. The capacitor dielectric layer has an edge terminus. A second capacit... | 03/16/2004 |
| 6703658 | Non-volatile semiconductor memory device and its manufacturing method In a non-volatile semiconductor memory device and a method for manufacturing the device, each memory cell and its select Tr have the same gate insulating film as a Vcc Tr. Further, the gate electrodes of a Vpp Tr and Vcc Tr are realized by the use of a fi... | 03/09/2004 |
| 6680502 | Buried digit spacer separated capacitor array The present invention relates to the field of semiconductor integrated circuits and, in particular, to capacitor arrays formed over the bit line of an integrated circuit substrate. The present invention provides a method for forming stacked capacitors, in... | 01/20/2004 |
| 6653739 | Semiconductor device A contact plug 26 formed between adjacent two wirings 14 according to a self-aligning manner is provided. An interlayer oxide film 12 is provided on a substrate layer 10 conductive to the bottom face of the contact plug. A lower insulating film 32 formed ... | 11/25/2003 |
| 6649962 | Selective polysilicon stud growth A memory cell having a bit line contact is provided. The memory cell may be a 6F2 memory cell. The bit line contact may have a contact hole bounded by insulating sidewalls, and the contact hole may be partially or completely filled with a doped... | 11/18/2003 |
| 6621110 | Semiconductor intergrated circuit device and a method of manufacture thereof A DRAM of an open bit line structure has a cell area smaller than that of a DRAM of a folded bit line structure and is susceptible to noise. A conventional DRAM of an open bit line structure has a large bit line capacitance and is susceptible to noise or ... | 09/16/2003 |
