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Pizza Pie With Concentric Rings of Crust
A pizza mold for forming a plurality of concentric raised ridges of dough (i.e., crust) on the surface of a pizza pie.
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| Number | Title | Issue Date |
| 7495349 | Self aligning electrode Electrodes are constructed with pressure-bonding techniques that simplify alignment of various electrode components during lamination. In an exemplary embodiment, a current collector is made from aluminum foil that has been roughed or pitted on both surfaces. The su... | 02/24/2009 |
| 7443032 | Memory device with chemical vapor deposition of titanium for titanium silicide contacts A titanium layer is formed on a substrate with chemical vapor deposition (CVD). First, a seed layer is formed on the substrate by combining a first precursor with a reducing agent by CVD. Then, the titanium layer is formed on the substrate by combining a second prec... | 10/28/2008 |
| 7425724 | Memory device and method of production and method of use of same and semiconductor device and method of production of same A memory device able to be produced without requiring high precision alignment, a method of production of the same, and a method of use of a memory device produced in this way, wherein a peripheral circuit portion (first semiconductor portion) formed by a first mini... | 09/16/2008 |
| 7378719 | Low leakage MIM capacitor Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a dielectric layer interposed between the bottom electrode and the top electrode. The capacitor structures ... | 05/27/2008 |
| 7375376 | Semiconductor display device and method of manufacturing the same A semiconductor display device with an interlayer insulating film in which surface levelness is ensured with a limited film formation time, heat treatment for removing moisture does not take long, and moisture in the interlayer insulating film is prevented from esca... | 05/20/2008 |
| 7348234 | Methods of forming capacitor constructions The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a si... | 03/25/2008 |
| 7288806 | DRAM arrays The invention includes memory arrays, and methods which can be utilized for forming memory arrays. A patterned etch stop can be used during memory array fabrication, with the etch stop covering storage node contact locations while leaving openings to bitline contact... | 10/30/2007 |
| 7282803 | Integrated electronic circuit comprising a capacitor and a planar interference inhibiting metallic screen An electronic circuit includes a substrate. A capacitor and at least one semiconductor component are supported by a surface of the substrate. A substantially planar screen, oriented parallel to the surface of the substrate and made of metallic material, is placed be... | 10/16/2007 |
| 7276750 | Semiconductor device having trench capacitor and fabrication method for the same A semiconductor device includes a semiconductor substrate with a trench; a capacitor; a collar oxide film arranged on a portion of a side of the trench above the capacitor; a storage node arranged on a side of the collar oxide film in an upper portion of the trench ... | 10/02/2007 |
| 7276725 | Bit line barrier metal layer for semiconductor device and process for preparing the same The present invention relates to a bit line barrier metal layer for a semiconductor device and a process for preparing the same, the process comprising: forming bit line contact on an insulation layer vapor-deposited on an upper part of a substrate so as to expose a... | 10/02/2007 |
| 7268384 | Semiconductor substrate having first and second pairs of word lines The invention includes methods of forming memory circuitry. In one implementation, a semiconductor substrate includes a pair of word lines having a bit node received therebetween. A bit node contact opening is formed within insulative material over the bit node. Sac... | 09/11/2007 |
| 7257043 | Isolation device over field in a memory device A memory device includes isolation devices located between-memory cells. A plurality of isolation lines connects the isolation devices to a positive voltage during normal operations but still keeps the isolation devices in the off state to provide isolation between ... | 08/14/2007 |
| 7247902 | Semiconductor device and method of manufacturing the same A semiconductor device comprises a first metal layer, which comprises a buried metal layer connected to a diffusion layer within a substrate or to a lower-layer wiring. A first metal wiring layer, a second metal layer having a buried metal layer, and a second metal ... | 07/24/2007 |
| 7226845 | Semiconductor constructions, and methods of forming capacitor devices The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conduc... | 06/05/2007 |
| 7199415 | Conductive container structures having a dielectric cap Container structures for use in integrated circuits and methods of their manufacture. The container structures have a dielectric cap on the top of a conductive container to reduce the risk of container-to-container shorting by insulating against bridging of conducti... | 04/03/2007 |
| 7170125 | Capacitor with electrodes made of ruthenium and method for patterning layers made of ruthenium or ruthenium A method for patterning layers made of ruthenium or ruthenium(IV) oxide and a capacitor comprising at least one electrode which is constructed from ruthenium or ruthenium(IV) oxide at least in sections. A layer made of ruthenium or ruthenium(IV) oxide is deposited o... | 01/30/2007 |
| 7135731 | Vertical DRAM and fabrication method thereof A vertical DRAM and fabrication method thereof. The vertical DRAM has a plurality of memory cells on a substrate, and each of the memory cells has a trench capacitor, a vertical transistor, and a source-isolation oxide layer in a deep trench. The main advantage of t... | 11/14/2006 |
| 7041896 | Housing for electronic apparatus The invention provides a housing for an electronic apparatus whose components can be worked through a reduced number of steps without deteriorating the shielding performance against electromagnetic waves. The housing for an electronic apparatus includes a plurality ... | 05/09/2006 |
| 7034408 | Memory device and method of manufacturing a memory device A memory device includes a DRAM memory cell array, which is implemented as a 6 F×F array, and peripheral circuitry. The word lines of the memory cell array are implemented as buried word lines, and, in addition, the bit lines including the bit line contacts are mad... | 04/25/2006 |
| 7034336 | Capacitorless 1-transistor DRAM cell and fabrication method The channel region (11) and the source-drain regions (9, 10) are arranged vertically at a sidewall of a dielectric trench filling (4). On the opposite side, the semiconductor material is bounded by the gate dielectric (18) and the gate el... | 04/25/2006 |
| 7022579 | Method for filling via with metal A method of filling vias for a PCRAM cell with a metal is described. A PCRAM intermediate structure including a substrate, a first conductor, and an insulator through which a via extends has a metallic material formed within the via and on a surface of the insulator... | 04/04/2006 |
| 7020039 | Isolation device over field in a memory device A memory device includes isolation devices located between memory cells. A plurality of isolation lines connects the isolation devices to a positive voltage during normal operations but still keeps the isolation devices in the off state to provide isolation between ... | 03/28/2006 |
| 6992343 | Semiconductor memory device A semiconductor memory device is provided which can achieve the high integration, ultra-high speed operation, and significant reduction of power consumption during the information holding time, by reducing the increase in the area of a memory cell and obtaining a pe... | 01/31/2006 |
| 6979849 | Memory cell having improved interconnect A memory cell having improved interconnect. Specifically, a dynamic random access memory (DRAM) based content addressable (CAM) memory cell is provided. The lower cell plate of the storage capacitor is implemented to provide an interconnect for the access transistor... | 12/27/2005 |
| 6967348 | Signal sharing circuit with microelectric die isolation features A signal sharing circuit includes a first pad adapted to receive a signal and a first sharing device associated with a first microelectronic die. The first sharing device is adapted to selectively share the signal with at least a second microelectronic die on one si... | 11/22/2005 |
| 6930341 | Integrated circuits including insulating spacers that extend beneath a conductive line Integrated circuit devices are fabricated by fabricating a conductive line on an insulating layer on an integrated circuit substrate. The conductive line includes a bottom adjacent the insulating layer, a top remote from the insulating layer and first and second sid... | 08/16/2005 |
| 6924524 | Integrated circuit memory devices An integrated circuit memory device and a method of manufacturing the same are provided. A plurality of word line structures are formed on predetermined portions of a semiconductor substrate on which an active region is defined. Word line contact plugs are formed be... | 08/02/2005 |
| 6903414 | Semiconductor memory having channel regions at sides of a trench Semiconductor memory and method for fabricating the same, the semiconductor memory including a cell transistor having a trench region formed in a semiconductor substrate and channel regions at sides of the trench region, source/drain regions formed in a bottom of th... | 06/07/2005 |
| 6900486 | Ferroelectric memory and method for manufacturing same Ferroelectric memory includes a hollow formed in a first insulation film. A lower electrode is formed in this hollow by sol-gel method including an application process due to a spin coat method. In this application process, a precursor solution is dripped on a surfa... | 05/31/2005 |
| 6882028 | Low leakage MIM capacitor Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a dielectric layer interposed between the bottom electrode and the top electrode. The capacitor structures ... | 04/19/2005 |
| 6872627 | Selective formation of metal gate for dual gate oxide application A new processing sequence is provided for the creation of a metal gate electrode. At least two polysilicon gate electrodes are provided over the surface of a substrate, these polysilicon gate electrodes having a relatively thick layer of gate dielectric making these... | 03/29/2005 |
| 6853052 | Semiconductor device having a buffer layer against stress A semiconductor device and a method for preparing the same that can solve crack of a semiconductor film, capacitance electrodes and the like due to stress when forming a source electrode and a drain electrode in a semiconductor device having a thin film transistor a... | 02/08/2005 |
| 6849959 | Method of fabricating semiconductor device A method of fabricating a semiconductor device according to the invention comprises forming a capacitor comprising a lower electrode formed on a semiconductor substrate, a capacitive insulator made up of a metal oxide film, formed on the lower electrode, and an uppe... | 02/01/2005 |
| 6849889 | Semiconductor device having storage node contact plug of DRAM (dynamic random access memory) A method for forming a storage node contact plug of a dynamic random access memory includes forming insulating layers on an overall surface of a semiconductor substrate having a plurality of buried contact plugs, etching the insulating layers down to a top surface o... | 02/01/2005 |
| 6847075 | Semiconductor integrated circuit apparatus and fabrication method thereof A semiconductor integrated circuit apparatus having a planar capacitor can use a plurality of source voltages therein. According to the semiconductor integrated circuit apparatus, it is possible to not only control thresholds of individual MOS transistors but also r... | 01/25/2005 |
| 6834019 | Isolation device over field in a memory device A memory device includes isolation devices located between memory cells. A plurality of isolation lines connects the isolation devices to a positive voltage during normal operations but still keeps the isolation devices in the off state to provide isolation between ... | 12/21/2004 |
| 6803669 | Integrated circuits having self-aligned metal contact structures A microelectronic contact structure, e.g., a contact structure for a capacitor electrode of a DRAM, comprises a first dielectric layer on a substrate, a conductive region disposed on a first dielectric layer, a second dielectric layer on the first dielectric layer a... | 10/12/2004 |
| 6797557 | Methods and systems for forming embedded DRAM for an MIM capacitor A method and system for fabricating a capacitor utilized in a semiconductor device. A salicide gate is designated for use with the semiconductor device. A self-aligned contact (SAC) may also be configured for use with the semiconductor device. The salicide gate and ... | 09/28/2004 |
| 6794705 | Multi-layer Pt electrode for DRAM and FRAM with high K dielectric materials A multi-layer electrode (246) and method of fabrication thereof in which a conductive region (244) is separated from a barrier layer (222) by a first conductive liner (240) and a second conductive liner (242). First conductive laye... | 09/21/2004 |
| 6791137 | Semiconductor integrated circuit device and process for manufacturing the same In semiconductor integrated circuit devices having fine memory cells and a reduced bit line capacity, a side wall insulating film of gate electrodes (word line) is made of silicon nitride and a side wall insulating film of silicon oxide having a dielectric constant ... | 09/14/2004 |
