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| Number | Title | Issue Date |
| 8188607 | Layout structure for chip coupling A layout structure disposed on the substrate of the liquid crystal display (LCD) for chip coupling is provided. The first and second orientations that are substantially perpendicular to the first orientation can be defined on the substrate. The layout structure incl... | 05/29/2012 |
| 8178980 | Bond pad structure A bonding pad structure is provided that includes two conductive layers and a connective layer interposing the two conductive layers. The connective layer includes a contiguous, conductive structure. In an embodiment, the contiguous conductive structure is a solid l... | 05/15/2012 |
| 8178981 | Semiconductor device The present invention aims at offering the semiconductor device which can improve the strength to the stress generated with a bonding pad. In the semiconductor device concerning the present invention, a plurality of bonding pads are formed on a semiconductor chip. I... | 05/15/2012 |
| 8169088 | Power converter integrated circuit floor plan and package For a DC to DC converter circuit integrated on a packaged die, the relative positions of various die pads and power MOSFETs on the die for a small outline integrated circuit package are described. ... | 05/01/2012 |
| 8159077 | Pad in semicondcutor device and fabricating method thereof A pad in a semiconductor device and fabricating method thereof are disclosed. The pad includes an uppermost metal layer first to Nth intermediate metal layers, wherein capacitors configured or formed by the uppermost metal layer and the first to Nth ... | 04/17/2012 |
| 8138617 | Apparatus and method for packaging circuits Methods for forming an edge contact on a die and edge contact structures are described. The edge contacts on the die do not increase the height of the die. The edge contacts are positioned on the periphery of a die. The edge contacts are positioned in the saw street... | 03/20/2012 |
| 8134241 | Electronic elements and devices with trench under bond pad feature Electronic elements having an active device region and bonding pad (BP) region on a common substrate desirably include a dielectric region underlying the BP to reduce the parasitic impedance of the BP and its interconnection as the electronic elements are scaled to ... | 03/13/2012 |
| 8129848 | Light emitting device having a plurality of light emitting cells connected in series and method of fabricating the same Disclosed are a light emitting device having a plurality of light emitting cells connected in series and a method of fabricating the same. The light emitting device includes a buffer layer formed on a substrate. A plurality of rod-shaped light emitting cells are loc... | 03/06/2012 |
| 8115325 | Semiconductor integrated circuit including plurality of bonding pads A semiconductor integrated circuit includes a plurality of bonding pads formed along an edge of a semiconductor substrate; a plurality of I/O cells arranged along the edge under the plurality of bonding pads; an upper layer wire mesh including a plurality of upper l... | 02/14/2012 |
| 8102062 | Optionally bonding either two sides or more sides of integrated circuits Methods and systems for forming a variety of integrated circuits, having quite different interfaces and packages, from a single manufactured die. Preferably the die has bond pads for at least a first mode of operation positioned along only two of its four sides, and... | 01/24/2012 |
| 8102063 | Pad structure with a nano-structured coating film A pad structure includes a copper circuit pattern on a substrate, at least a gold layer stacked on the copper circuit pattern, and a nano-structured coating film stacked on the gold layer. ... | 01/24/2012 |
| 8097962 | Semiconductor device A semiconductor device includes a substrate having external connection terminals, and a semiconductor chip mounted over a semiconductor-chip mounting portion of the substrate. The external connection terminals are formed by sequentially forming an electroless nickel... | 01/17/2012 |
| 8097963 | Electrically conductive matrix for z-axis interconnect An IC package including one or more z-axis interconnects for performing at least in part the fan-in/fan out interconnection for electrically coupling contacts of semiconductor die to external contacts of the package. The z-axis interconnect comprises a matrix of ele... | 01/17/2012 |
| 8097964 | IC having TSV arrays with reduced TSV induced stress An integrated circuit (IC) includes a substrate having a top side having active circuitry thereon including a plurality of metal interconnect levels including a first metal interconnect level and a top metal interconnect level, and a bottom side. At least one TSV ar... | 01/17/2012 |
| 8076787 | Semiconductor device, manufacturing method thereof, and manufacturing method of semiconductor module An improvement is achieved in the mounting reliability of a semiconductor device. A semiconductor chip is mounted over an upper surface of a wiring substrate. A plurality of solder balls are disposed individually over a plurality of lands formed on a lower surface o... | 12/13/2011 |
| 8076788 | Off-chip vias in stacked chips A microelectronic assembly includes first and second stacked microelectronic elements, each having spaced apart traces extending along a front face and beyond at least a first edge thereof. An insulating region can contact the edges of each microelectronic element a... | 12/13/2011 |
| 8076786 | Semiconductor package and method for packaging a semiconductor package A wire bonding structure includes a chip and a bonding wire. The chip includes a base material, at least one first metallic pad, a re-distribution layer and at least one second metallic pad. The first metallic pad is disposed on the base material. The re-distributio... | 12/13/2011 |
| 8063497 | Liquid crystal display A chip having a bump layout suitable for the chip on glass technology and a driving IC includes a plurality of first bumps and a plurality of second bumps for electrically connecting to a glass substrate of a displayer. The first and second bumps are disposed on a s... | 11/22/2011 |
| 8058735 | Wafer-level chip scale package having stud bump and method for fabricating the same A wafer level chip scale package having stud bumps and a method for fabricating the same are described. The wafer level chip scale package includes a silicon substrate having a passivation layer and a chip pad on its top surface; a stud bump being formed on the chip... | 11/15/2011 |
| 8044523 | Semiconductor device The invention relates to a semiconductor device with a semiconductor chip, on which a terminal contact formed in one piece, a patterned metallization layer, contacting the terminal contact, and a connecting layer are successively arranged, the patterned metallizatio... | 10/25/2011 |
| 8030783 | Integrated circuit package with open substrate A method of manufacturing an integrated circuit package includes: forming a substrate that includes: forming a core layer, forming vias in the core layer, and forming a conductive layer having a predetermined thickness on the core layer and having substantially twic... | 10/04/2011 |
| 8026616 | Printed circuit board, semiconductor package, card apparatus, and system A printed circuit board providing high reliability using a packaging of high capacity semiconductor chip, a semiconductor package, and a card and a system using the semiconductor package. The semiconductor package includes a substrate having a first surface and a se... | 09/27/2011 |
| 8026617 | Contact layout structure A contact layout structure includes a substrate having at least a first region defined thereon, plural sets of first contact layouts positioned along a predetermined direction in the first region, and a plurality of second contact layouts positioned in the first reg... | 09/27/2011 |
| 8013455 | Semiconductor device having pads A semiconductor device having pads is provided. The semiconductor device includes first pads formed along a first row, and second pads formed along a second row. The first via contact portions extending from the first pads toward the second row, and second via conta... | 09/06/2011 |
| 8008786 | Dynamic pad size to reduce solder fatigue A semiconductor device is provided which comprises a substrate (501) having a plurality of bond pads (503) disposed thereon. Each bond pad has a major axis and a minor axis in a direction parallel to the substrate, and the ratio of the major axis to th... | 08/30/2011 |
| 7999397 | Microelectronic packages and methods therefor A microelectronic package includes a microelectronic element having faces and contacts, the microelectronic element having an outer perimeter, and a substrate overlying and spaced from a first face of the microelectronic element, whereby an outer region of the subst... | 08/16/2011 |
| 7989963 | Transistor circuit formation substrate A specially designed mask controls the arrangement of conductive materials that form a source and drain of a transistor. Designing the mask can be costly and time-consuming, which means that the testing of a circuit involving a transistor can also be costly, time co... | 08/02/2011 |
| 7989964 | Semiconductor integrated circuit On a semiconductor chip in a semiconductor integrated circuit, a plurality of circuit cells each of which has a pad are formed along a first chip side of the semiconductor chip. Among the plurality of circuit cells, one or more circuit cells at least in the vicinity... | 08/02/2011 |
| 7982321 | Apparatus and method for preventing configurable system-on-a-chip integrated circuits from beginning I/O limited An integrated circuit containing multiple modules coupled to a pad via a multiplexer. The modules are selectively coupled to the pad by the multiplexer to provide integrated circuit function flexibility with a limited number of pads. A multiplexer select signal dete... | 07/19/2011 |
| 7977805 | Flexible wiring substrate, semiconductor device and electronic device using flexible wiring substrate, and fabricating method of flexible wiring substrate A flexible wiring substrate is provided which realizes a fine pitch of a wiring pattern and improves mechanical strength of the wiring pattern so as to prevent breaks or exfoliation of the wiring pattern. A flexible wiring substrate 3 of the present invention... | 07/12/2011 |
| 7964976 | Layered chip package and method of manufacturing same A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. The plurality of layer portions include at least one layer portion of a first type and at least one layer portion of a second... | 06/21/2011 |
| 7956474 | Structures, architectures, systems, methods, algorithms and software for configuring an integrated circuit for multiple packaging types Structures, architectures, systems, an integrated circuit, methods and software for configuring an integrated circuit for multiple packaging types and/or selecting one of a plurality of packaging types for an integrated circuit. The structure generally comprises a b... | 06/07/2011 |
| 7948094 | Semiconductor device The semiconductor device according to the present invention includes a semiconductor layer, an interlayer dielectric film formed on the semiconductor layer, a wire formed on the interlayer dielectric film with a metallic material to have a width of not more than 0.4... | 05/24/2011 |
| 7944060 | Device package structure, device packaging method, droplet ejection head, connector, and semiconductor device A device package structure includes: a base body having a conductive connection portion and a level difference portion; a device arranged on the base body, having a connection terminal electrically connected to the conductive connection portion via the level differe... | 05/17/2011 |
| 7932616 | Semiconductor device sealed in a resin section and method for manufacturing the same A semiconductor device includes a first semiconductor chip having a pad electrode formed on an upper surface thereof; a resin section sealing the first semiconductor chip with the upper surface and a side surface of the first semiconductor chip being covered and a l... | 04/26/2011 |
| 7932615 | Electronic devices including solder bumps on compliant dielectric layers An electronic device may include a substrate with an input/output pad thereon, and a compliant dielectric layer on a first portion of the substrate such that a second portion of the substrate is free of the compliant dielectric layer. A conductive redistribution lin... | 04/26/2011 |
| 7928589 | Semiconductor device The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transisto... | 04/19/2011 |
| 7928588 | Circuit signal connection interface, a manufacture method thereof, and an electronic device using the same A circuit signal connection interface, a manufacturing method thereof, and an electronic device using the same are provided. The circuit signal connection interface includes a first signal line and a second signal line juxtaposed to each other, an insulation layer, ... | 04/19/2011 |
| 7915745 | Multi-port memory device having serial input/output interface A multi-port memory device includes a first package ball out region in which a plurality of balls for a serial I/O interface part are arranged; and a second package ball out region in which a plurality of balls for a dynamic random access memory (DRAM) part are arra... | 03/29/2011 |
| 7911069 | Semiconductor device and layout method thereof A semiconductor device and a layout method thereof are provided, each of which contributes to a reduction in layout area and appropriately adjusts an inter-wiring capacitance even where wiring widths and intervals in a plurality of wiring layers differ at a bus wiri... | 03/22/2011 |
