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| Number | Title | Issue Date |
| 8338954 | Semiconductor apparatus and fabrication method thereof A semiconductor apparatus includes an aluminum electrode film formed on a semiconductor chip; and a nickel plated layer formed on the aluminum electrode film, wherein a concentration of sodium and potassium present in the nickel plated layer and at an interface betw... | 12/25/2012 |
| 8288867 | Semiconductor constructions Some embodiments include semiconductor processing methods in which a copper barrier is formed to be laterally offset from a copper component, and in which nickel is formed to extend across both the barrier and the component. The barrier may extend around an entire l... | 10/16/2012 |
| 8022550 | Semiconductor integrated circuit device Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections ... | 09/20/2011 |
| 7701061 | Semiconductor device with solder balls having high reliability A semiconductor device includes a substrate, a metal layer, an alloy layer and a Sn—Ag—Cu-based solder ball. The metal layer is configured to be formed on the substrate. The alloy layer is configured to be formed on the metal layer. The Sn—Ag—Cu-based solder... | 04/20/2010 |
| 7638879 | Semiconductor package and fabrication method thereof A semiconductor package and a fabrication method are disclosed. The fabrication method includes applying a sacrificial layer on one surface of a metal carrier, applying an insulation layer on the sacrificial layer, and forming through holes in the sacrificial layer ... | 12/29/2009 |
| 7470993 | Semiconductor component with passivation layer A semiconductor component has a semiconductor body and also a metal/insulation structure arranged above the semiconductor body and having a plurality of metal regions and insulation regions laterally adjoining one another. The metal regions serve for supplying the s... | 12/30/2008 |
| 7432584 | Leadframe for use in a semiconductor package A leadframe comprises a die mounting area, a plurality of lead fingers and a metal deposit having a negative electrochemical potential with respect to a standard H2 half cell. A semiconductor package comprises the leadframe and a semiconductor chip having... | 10/07/2008 |
| 7411303 | Semiconductor assembly having substrate with electroplated contact pads An apparatus comprising an insulating substrate having first and second surfaces and a plurality of metal-filled vias extending from the first to the second surface. The first and second surfaces have contact pads, each one comprising a connector stack to at least o... | 08/12/2008 |
| 7410899 | Defectivity and process control of electroless deposition in microelectronics applications Methods and compositions for electrolessly depositing Co, Ni, or alloys thereof onto a substrate in manufacture of microelectronic devices. Grain refiners, levelers, oxygen scavengers, and stabilizers for electroless Co and Ni deposition solutions. ... | 08/12/2008 |
| 7385294 | Semiconductor device having nickel silicide and method of fabricating nickel silicide A semiconductor device having nickel silicide and a method for fabricating nickel silicide. A semiconductor substrate having a plurality of doped regions is provided. Subsequently, a nickel layer is formed on the semiconductor substrate, and a first rapid thermal pr... | 06/10/2008 |
| 7375414 | High permeability layered films to reduce noise in high speed interconnects This invention provides a structure and method for improved transmission line operation on integrated circuits. One method of the invention includes forming transmission lines in an integrated circuit. The method includes forming a first layer of electrically conduc... | 05/20/2008 |
| 7368326 | Methods and apparatus to reduce growth formations on plated conductive leads A process includes annealing one or more plated conductive leads at a predetermined temperature. The one or more plated conductive leads are plated with one or more layers, where each layer comprises a material. The predetermined temperature is greater than or equal... | 05/06/2008 |
| 7358170 | Methods of forming conductive interconnects, and methods of depositing nickel The invention includes methods of electroless plating of nickel selectively on exposed conductive surfaces relative to exposed insulative surfaces. The electroless plating can utilize a bath which contains triethanolamine, maleic anhydride and at least one nickel sa... | 04/15/2008 |
| 7352055 | Semiconductor package with controlled solder bump wetting A semiconductor package includes a substrate having a plurality of lead fingers. A plurality of stud bumps is attached to the plurality of lead fingers. A die having a plurality solder bumps is provided. The plurality of solder bumps is attached to the plurality of ... | 04/01/2008 |
| 7347349 | Apparatus and method for printing micro metal structures A method and device for printing liquid material such as liquid solder is provided. C4 structures as small as 10 microns in diameter can be produced using devices and methods described above. Further, devices and methods provided are able to operate at temperatures ... | 03/25/2008 |
| 7339267 | Semiconductor package and method for forming the same Semiconductor packages (100) that prevent the leaching of gold from back metal layers (118) into the solder (164) and methods for fabricating the same are provided. An exemplary method comprises providing a semiconductor wafer stack (110)... | 03/04/2008 |
| 7339262 | Tape circuit substrate and semiconductor apparatus employing the same A tape circuit substrate and semiconductor apparatus employing the same, and a method for forming a tape circuit substrate may reduce or eliminate electromagnetic interference (EMI) and provide a substrate or apparatus which can supply a more stable power supply vol... | 03/04/2008 |
| 7309885 | PRAMs having a plurality of active regions located vertically in sequence and methods of forming the same There are provided PRAMS having a plurality of active regions located vertically in sequence and methods of forming the same. The PRAM and the method provide an approach to rapidly changing phase in a phase change layer pattern with a given design rule. A semiconduc... | 12/18/2007 |
| 7303988 | Methods of manufacturing multi-level metal lines in semiconductor devices Methods of forming a multi-level metal line of a semiconductor device are disclosed. One example method includes subsequently stacking first and second metal layers, wherein a conductive etching stopper layer is interposed at an interface between the first and secon... | 12/04/2007 |
| 7274091 | Semiconductor device and method of manufacturing a semiconductor device There is provided a semiconductor device including, a bed, a brazing filler metal formed on a first surface of the bed, a barrier metal film formed on a first surface of the brazing filler metal, a alloy film formed on a first surface of the barrier metal film, a se... | 09/25/2007 |
| 7268425 | Thermally enhanced electronic flip-chip packaging with external-connector-side die and method A method and apparatus for making a package having improved heat conduction characteristics and high frequency response. A relatively thick package substrate, such as copper, has a wiring layer bonded to one face, leaving the opposite face exposed, for example, to b... | 09/11/2007 |
| 7256491 | Thermal interconnect systems methods of production and uses thereof A thermal transfer material is described herein that includes: a heat spreader component, wherein the heat spreader component comprises a top surface, a bottom surface and at least one heat spreader material, and at least one solder material, wherein the solder mate... | 08/14/2007 |
| 7253501 | High performance metallization cap layer A semiconductor device having a nonconductive cap layer comprising a first metal element. The nonconductive cap layer comprises a first metal nitride, a first metal oxide, or a first metal oxynitride over conductive lines and an insulating material between the condu... | 08/07/2007 |
| 7253519 | Chip packaging structure having redistribution layer with recess A chip structure comprising a chip, a redistribution layer, a second passivation layer and at least a bump is provided. The chip has a first passivation layer and at least a bonding pad. The first passivation layer exposes the bonding pad and has at least a recess. ... | 08/07/2007 |
| 7250685 | Etched leadframe flipchip package system The present invention provides an etched leadframe flipchip package system comprising forming a leadframe comprises forming contact leads and etching a plurality of multiple dotted grooves on the contact leads, and attaching a flipchip integrated circuit having sold... | 07/31/2007 |
| 7250682 | Semiconductor integrated circuit device Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections ... | 07/31/2007 |
| 7247915 | Cobalt/nickel bi-layer silicide process for very narrow line polysilicon gate technology A silicide method for integrated circuit and semiconductor device fabrication wherein a layer of nickel is formed over at least one silicon region of a substrate and a layer of cobalt is formed over the nickel layer. The cobalt/nickel bi-layer is then annealed to tr... | 07/24/2007 |
| 7239025 | Selective deposition of solder ball contacts Methods of forming solder ball contacts having dimensions of approximately 2.5 microns in diameter for use in C4-type connections. The methods form solder ball contacts using selective deposition of solder on metal contact pads of a device. The metal contact pads ha... | 07/03/2007 |
| 7233072 | Electronic part and surface treatment method of the same There is provided a surface treatment method for an electronic part, which uses a metal not containing lead and tin and having excellent solder wettability, is economical and has high reliability. In the surface treatment method for the electronic part in which a so... | 06/19/2007 |
| 7227231 | Semiconductor integrated circuit device A semiconductor integrated circuit device has a first MOS transistor and a second MOS transistor. The first MOS transistor has a first source, a first gate electrode, and a first wiring metal connected to the first source and overlapping the first gate electrode. Th... | 06/05/2007 |
| 7223689 | Methods for forming a metal contact in a semiconductor device in which an ohmic layer is formed while forming a barrier metal layer A metal contact in a semiconductor device is formed by forming an insulating layer having a contact hole therein on a silicon substrate. A cobalt layer is formed on a bottom and inner walls of the contact hole. A cobalt silicide layer is formed at the bottom of the ... | 05/29/2007 |
| 7224066 | Bonding material and circuit device using the same A circuit device is provided in which the bonding reliability of a brazing material such as soft solder is improved. A circuit device of the present invention includes conductive patterns, a bonding material which fixes circuit elements to the conductive patterns, a... | 05/29/2007 |
| 7208828 | Semiconductor package with wire bonded stacked dice and multi-layer metal bumps A semiconductor package includes a substrate formed of a board material, a semiconductor die bonded to the substrate, and an encapsulant on the die. The package also includes an array of external contacts formed as multi layered metal bumps that include a base layer... | 04/24/2007 |
| 7202556 | Semiconductor package having substrate with multi-layer metal bumps A semiconductor package includes a substrate formed of a board material, a semiconductor die bonded to the substrate, and an encapsulant on the die. The package also includes an array of external contacts formed as multi layered metal bumps that include a base layer... | 04/10/2007 |
| 7191515 | Method for manufacturing an interconnected circuit board assembly An electrical assembly (200, FIG. 2) is formed from two, interconnected circuit boards (202, 204). Conductive spacers (240) and a conductive material (260) are placed between complementary bond pads (218, 232) on the circuit... | 03/20/2007 |
| 7186636 | Nickel bonding cap over copper metalized bondpads A method for forming a nickel cap layer over copper metalized bond pad is disclosed in which the phosphorous content of the nickel cap, and particularly the surface of the nickel cap, may be controlled. The phosphorous content of the surface of the nickel cap is sui... | 03/06/2007 |
| 7166921 | Aluminum alloy film for wiring and sputter target material for forming the film Disclosed is an Al alloy film for wiring, which consists of, by atom, 0.2 to 1.5% Ge and 0.2 to 2.5% Ni and the balance being essentially Al, wherein a total amount of Ge and Ni is not more than 3.0%. The invention is also directed to a sputter target material havin... | 01/23/2007 |
| 7164205 | Semiconductor carrier film, and semiconductor device and liquid crystal module using the same A semiconductor carrier film includes (i) a base film having insulating property, (ii) a barrier layer provided on the base film, the barrier layer including nickel-chrome alloy as a main component, and (iii) a wire layer provided on the barrier layer, the wire laye... | 01/16/2007 |
| 7154180 | Electronic device, method of manufacture of the same, and sputtering target In an electronic device comprising a first electrodes consisting of a metal oxide and a second electrode consisting of an aluminum alloy film directly contacted and electrically connected to the first electrode, the contact interface between the aluminum alloy film ... | 12/26/2006 |
| 7148086 | Semiconductor package with controlled solder bump wetting and fabrication method therefor A semiconductor package and a method of manufacturing a semiconductor package include a substrate having a plurality of lead fingers. A plurality of stud bumps is attached to the plurality of lead fingers. A die having a plurality solder bumps is provided. The plura... | 12/12/2006 |
